add.fit.rpt

vhdl 学习基础实例,有利于VHDL入门很有帮助

; Name                                                                           ; Value  ;
+--------------------------------------------------------------------------------+--------+
; Mid Wire Use - Fit Attempt 1                                                   ; 1      ;
; Mid Slack - Fit Attempt 1                                                      ; -10757 ;
; Internal Atom Count - Fit Attempt 1                                            ; 12     ;
; LE/ALM Count - Fit Attempt 1                                                   ; 12     ;
; LAB Count - Fit Attempt 1                                                      ; 2      ;
; Outputs per Lab - Fit Attempt 1                                                ; 5.500  ;
; Inputs per LAB - Fit Attempt 1                                                 ; 6.000  ;
; Global Inputs per LAB - Fit Attempt 1                                          ; 0.000  ;
; LAB Constraint 'non-global clock / CE pair + async load' - Fit Attempt 1       ; 0:2    ;
; LAB Constraint 'ce + sync load' - Fit Attempt 1                                ; 0:2    ;
; LAB Constraint 'non-global controls' - Fit Attempt 1                           ; 0:2    ;
; LAB Constraint 'un-route combination' - Fit Attempt 1                          ; 0:2    ;
; LAB Constraint 'non-global with asyn_clear' - Fit Attempt 1                    ; 0:2    ;
; LAB Constraint 'un-route with async_clear' - Fit Attempt 1                     ; 0:2    ;
; LAB Constraint 'non-global async clear + sync clear' - Fit Attempt 1           ; 0:2    ;
; LAB Constraint 'global non-clock/non-asynch_clear' - Fit Attempt 1             ; 0:2    ;
; LAB Constraint 'ygr_cl_ngclk_gclkce_sload_aload_constraint' - Fit Attempt 1    ; 0:2    ;
; LAB Constraint 'global control signals' - Fit Attempt 1                        ; 0:2    ;
; LAB Constraint 'clock / ce pair constraint' - Fit Attempt 1                    ; 0:2    ;
; LAB Constraint 'aload_aclr pair with aload used' - Fit Attempt 1               ; 0:2    ;
; LAB Constraint 'aload_aclr pair' - Fit Attempt 1                               ; 0:2    ;
; LAB Constraint 'sload_sclear pair' - Fit Attempt 1                             ; 0:2    ;
; LAB Constraint 'invert_a constraint' - Fit Attempt 1                           ; 1:2    ;
; LAB Constraint 'has placement constraint' - Fit Attempt 1                      ; 0:2    ;
; LAB Constraint 'use of ADATA or SDATA by registers constraint' - Fit Attempt 1 ; 0:2    ;
; LEs in Chains - Fit Attempt 1                                                  ; 0      ;
; LEs in Long Chains - Fit Attempt 1                                             ; 0      ;
; LABs with Chains - Fit Attempt 1                                               ; 0      ;
; LABs with Multiple Chains - Fit Attempt 1                                      ; 0      ;
; Time - Fit Attempt 1                                                           ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1                                            ; 0.015  ;
+--------------------------------------------------------------------------------+--------+


+----------------------------------------------+
; Advanced Data - Placement                    ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Wire Use - Fit Attempt 1      ; 0      ;
; Early Slack - Fit Attempt 1         ; -13471 ;
; Mid Wire Use - Fit Attempt 1        ; 1      ;
; Mid Slack - Fit Attempt 1           ; -11624 ;
; Late Wire Use - Fit Attempt 1       ; 1      ;
; Late Slack - Fit Attempt 1          ; -11624 ;
; Peak Regional Wire - Fit Attempt 1  ; 0.000  ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.031  ;
+-------------------------------------+--------+


+----------------------------------------------+
; Advanced Data - Routing                      ;
+-------------------------------------+--------+
; Name                                ; Value  ;
+-------------------------------------+--------+
; Early Slack - Fit Attempt 1         ; -10635 ;
; Early Wire Use - Fit Attempt 1      ; 1      ;
; Peak Regional Wire - Fit Attempt 1  ; 1      ;
; Mid Slack - Fit Attempt 1           ; -11499 ;
; Late Slack - Fit Attempt 1          ; -11499 ;
; Late Slack - Fit Attempt 1          ; -11499 ;
; Late Wire Use - Fit Attempt 1       ; 0      ;
; Time - Fit Attempt 1                ; 0      ;
; Time in tsm_tan.dll - Fit Attempt 1 ; 0.016  ;
+-------------------------------------+--------+


+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
    Info: Version 8.0 Build 215 05/29/2008 SJ Full Version
    Info: Processing started: Mon Apr 20 14:12:11 2009
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off add -c add
Info: Selected device EPM1270T144C5 for design "add"
Info: Fitter is performing a Standard Fit compilation using maximum Fitter effort to optimize design performance
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
    Info: Device EPM570T144C5 is compatible
    Info: Device EPM570T144I5 is compatible
    Info: Device EPM570T144A5 is compatible
    Info: Device EPM1270T144I5 is compatible
    Info: Device EPM1270T144A5 is compatible
Info: Completed User Assigned Global Signals Promotion Operation
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
    Info: Assuming a global fmax requirement of 1000 MHz
    Info: Assuming a global tsu requirement of 2.0 ns
    Info: Assuming a global tco requirement of 1.0 ns
    Info: Assuming a global tpd requirement of 1.0 ns
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished register packing
Info: Fitter preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Estimated most critical path is pin to pin delay of 12.124 ns
    Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_71; Fanout = 3; PIN Node = 'a[0]'
    Info: 2: + IC(3.679 ns) + CELL(0.200 ns) = 5.011 ns; Loc. = LAB_X13_Y7; Fanout = 2; COMB Node = 'Add0~309'
    Info: 3: + IC(0.269 ns) + CELL(0.914 ns) = 6.194 ns; Loc. = LAB_X13_Y7; Fanout = 7; COMB Node = 'Add0~311'
    Info: 4: + IC(0.983 ns) + CELL(0.200 ns) = 7.377 ns; Loc. = LAB_X13_Y7; Fanout = 1; COMB Node = 'Mux2~3'
    Info: 5: + IC(2.425 ns) + CELL(2.322 ns) = 12.124 ns; Loc. = PIN_111; Fanout = 0; PIN Node = 'c[5]'
    Info: Total cell delay = 4.768 ns ( 39.33 % )
    Info: Total interconnect delay = 7.356 ns ( 60.67 % )
Info: Fitter routing operations beginning
Info: Average interconnect usage is 0% of the available device resources
    Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X9_Y0 to location X17_Y11
Info: Fitter routing operations ending: elapsed time is 00:00:00
Warning: Following 9 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results
    Info: Pin c[0] has VCC driving its datain port
    Info: Pin en[0] has GND driving its datain port
    Info: Pin en[1] has VCC driving its datain port
    Info: Pin en[2] has VCC driving its datain port
    Info: Pin en[3] has VCC driving its datain port
    Info: Pin en[4] has VCC driving its datain port
    Info: Pin en[5] has VCC driving its datain port
    Info: Pin en[6] has VCC driving its datain port
    Info: Pin en[7] has VCC driving its datain port
Info: Generated suppressed messages file C:/altera/80/quartus/vhdl/basicexperiment/adder/add.fit.smsg
Info: Quartus II Fitter was successful. 0 errors, 1 warning
    Info: Peak virtual memory: 178 megabytes
    Info: Processing ended: Mon Apr 20 14:12:15 2009
    Info: Elapsed time: 00:00:04
    Info: Total CPU time (on all processors): 00:00:02


+----------------------------+
; Fitter Suppressed Messages ;
+----------------------------+
The suppressed messages can be found in C:/altera/80/quartus/vhdl/basicexperiment/adder/add.fit.smsg.