add.map.summary

vhdl 学习基础实例,有利于VHDL入门很有帮助

Analysis & Synthesis Status : Successful - Mon Apr 20 14:12:09 2009
Quartus II Version : 8.0 Build 215 05/29/2008 SJ Full Version
Revision Name : add
Top-level Entity Name : add
Family : MAX II
Total logic elements : 12
Total pins : 22
Total virtual pins : 0
Total memory bits : 0
DSP block 9-bit elements : 0
Total PLLs : 0
Total DLLs : 0