add.sdc

vhdl 学习基础实例,有利于VHDL入门很有帮助

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# Generated by : Version 8.0 Build 215 05/29/2008 SJ Full Version
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# Project      : add
# Revision     : add
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# Date         : Fri Apr 17 15:40:53 中国标准时间 2009
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# WARNING: Expected ENABLE_CLOCK_LATENCY to be set to 'ON', but it is set to 'OFF'
#          In SDC, create_generated_clock auto-generates clock latency
# WARNING: Expected ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS to be set to 'ON', but it is set to 'OFF'
#          Latches are always treated as synchronous elements by the TimeQuest Timing Analyzer
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# Create generated clocks based on PLLs
derive_pll_clocks -use_tan_name
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# ** Clock Latency
#    -------------

# ** Clock Uncertainty
#    -----------------

# ** Multicycles
#    -----------
# ** Cuts
#    ----

# ** Input/Output Delays
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# ** Tpd requirements
#    ----------------

# ** Setup/Hold Relationships
#    ------------------------

# ** Tsu/Th requirements
#    -------------------


# ** Tco/MinTco requirements
#    -----------------------



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