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📄 add.fit.eqn

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-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--A1L5 is add~308 at LC_X15_Y7_N5
--operation mode is normal

A1L5 = b[0] $ a[0];


--A1L6 is add~309 at LC_X14_Y7_N5
--operation mode is normal

A1L6 = b[1] $ a[1] $ (b[0] & a[0]);


--A1L7 is add~310 at LC_X14_Y7_N2
--operation mode is normal

A1L7 = b[1] & (a[1] # b[0] & a[0]) # !b[1] & a[1] & b[0] & a[0];


--A1L8 is add~311 at LC_X14_Y7_N0
--operation mode is normal

A1L8 = a[2] $ b[2] $ A1L7;


--A1L9 is add~312 at LC_X14_Y7_N3
--operation mode is normal

A1L9 = a[2] & (b[2] # A1L7) # !a[2] & b[2] & A1L7;


--A1L23 is Mux~28 at LC_X14_Y7_N7
--operation mode is normal

A1L23 = A1L5 & (A1L9 # A1L8 $ A1L6) # !A1L5 & (A1L6 # A1L9 $ A1L8);


--A1L33 is Mux~29 at LC_X11_Y10_N2
--operation mode is normal

A1L33 = A1L6 & !A1L9 & (A1L5 # !A1L8) # !A1L6 & A1L5 & (A1L8 $ !A1L9);


--A1L43 is Mux~30 at LC_X14_Y7_N1
--operation mode is normal

A1L43 = A1L6 & !A1L9 & A1L5 # !A1L6 & (A1L8 & !A1L9 # !A1L8 & (A1L5));


--A1L53 is Mux~31 at LC_X14_Y7_N8
--operation mode is normal

A1L53 = A1L5 & (A1L6 $ !A1L8) # !A1L5 & (A1L6 & !A1L8 & A1L9 # !A1L6 & A1L8 & !A1L9);


--A1L63 is Mux~32 at LC_X14_Y7_N6
--operation mode is normal

A1L63 = A1L9 & A1L8 & (A1L6 # !A1L5) # !A1L9 & !A1L5 & !A1L8 & A1L6;


--A1L73 is Mux~33 at LC_X14_Y7_N9
--operation mode is normal

A1L73 = A1L6 & (A1L5 & (A1L9) # !A1L5 & A1L8) # !A1L6 & A1L8 & (A1L5 $ A1L9);


--A1L83 is Mux~34 at LC_X14_Y7_N4
--operation mode is normal

A1L83 = A1L8 & !A1L6 & (A1L5 $ !A1L9) # !A1L8 & A1L5 & (A1L6 $ !A1L9);


--b[0] is b[0] at PIN_67
--operation mode is input

b[0] = INPUT();


--a[0] is a[0] at PIN_71
--operation mode is input

a[0] = INPUT();


--a[1] is a[1] at PIN_69
--operation mode is input

a[1] = INPUT();


--b[1] is b[1] at PIN_63
--operation mode is input

b[1] = INPUT();


--a[2] is a[2] at PIN_68
--operation mode is input

a[2] = INPUT();


--b[2] is b[2] at PIN_62
--operation mode is input

b[2] = INPUT();


--c[0] is c[0] at PIN_120
--operation mode is output

c[0] = OUTPUT(VCC);


--c[1] is c[1] at PIN_119
--operation mode is output

c[1] = OUTPUT(!A1L23);


--c[2] is c[2] at PIN_117
--operation mode is output

c[2] = OUTPUT(A1L33);


--c[3] is c[3] at PIN_114
--operation mode is output

c[3] = OUTPUT(A1L43);


--c[4] is c[4] at PIN_113
--operation mode is output

c[4] = OUTPUT(A1L53);


--c[5] is c[5] at PIN_111
--operation mode is output

c[5] = OUTPUT(A1L63);


--c[6] is c[6] at PIN_108
--operation mode is output

c[6] = OUTPUT(A1L73);


--c[7] is c[7] at PIN_109
--operation mode is output

c[7] = OUTPUT(A1L83);


--en[0] is en[0] at PIN_134
--operation mode is output

en[0] = OUTPUT(GND);


--en[1] is en[1] at PIN_133
--operation mode is output

en[1] = OUTPUT(VCC);


--en[2] is en[2] at PIN_124
--operation mode is output

en[2] = OUTPUT(VCC);


--en[3] is en[3] at PIN_123
--operation mode is output

en[3] = OUTPUT(VCC);


--en[4] is en[4] at PIN_121
--operation mode is output

en[4] = OUTPUT(VCC);


--en[5] is en[5] at PIN_125
--operation mode is output

en[5] = OUTPUT(VCC);


--en[6] is en[6] at PIN_131
--operation mode is output

en[6] = OUTPUT(VCC);


--en[7] is en[7] at PIN_132
--operation mode is output

en[7] = OUTPUT(VCC);


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