📄 84_4.15.txt
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--clk是clk2的两倍
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity eighttofour is
port (
clk: IN STD_LOGIC; --8 bit clock
TXC: IN std_logic;
reset: in std_logic;
data_in: in STD_LOGIC_VECTOR (7 DOWNTO 0) ;
TXEN: in std_logic; --buffer
TXD: out STD_LOGIC_VECTOR (3 DOWNTO 0) );
end eighttofour;
architecture Behavioral of eighttofour is
signal aa : STD_LOGIC_VECTOR(3 Downto 0);
signal bb : STD_LOGIC_VECTOR(3 Downto 0);
signal cc : STD_LOGIC_VECTOR(3 Downto 0);
signal count : STD_LOGIC;
begin
process(TXC, reset)
begin
if (reset = '0') then
count <= '0';
elsif (TXC'event and TXC ='1') then
count<= not count;
end if;
end process;
process(clk, reset,TXEN)
begin
if (reset = '0') then
aa <= (others => '0');
bb <= (others => '0');
elsif (clk'event and clk ='1') then
if(TXEN='1') then
bb(3) <= data_in(7);
bb(2) <= data_in(6);
bb(1) <= data_in(5);
bb(0) <= data_in(4);
aa(3) <= data_in(3);
aa(2) <= data_in(2);
aa(1) <= data_in(1);
aa(0) <= data_in(0);
end if;
end if;
end process;
process(TXC)
begin
if (reset = '0') then
cc<= (others => '0');
elsif (TXC'event and TXC ='1') then
if (count = '0') then
cc<=aa;
else cc <=bb;
end if;
end if;
end process;
TXD<=cc;
end Behavioral;
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