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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ENABLE IS
PORT(
CLK: IN STD_LOGIC;
RESET: IN STD_LOGIC;
CS: IN STD_LOGIC;
ADDR: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
DRIVE: OUT STD_LOGIC );
END ENABLE;
ARCHITECTURE BEHAVE OF ENABLE IS
BEGIN
PROCESS(CLK,RESET,ADDR,CS)
BEGIN
IF CLK'EVENT AND CLK ='1' THEN
IF RESET='0' AND CS='0' AND ADDR="101" THEN
DRIVE<='1';
ELSE DRIVE<='0';
END IF;
END IF;
END PROCESS;
END BEHAVE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CTRL IS
PORT (
CLK:IN STD_LOGIC;
EN: IN STD_LOGIC;
RW: IN STD_LOGIC;
RDY:IN STD_LOGIC;
TR: OUT STD_LOGIC;
DIN:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
PD: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
END CTRL;
ARCHITECTURE BEHAVE OF CTRL IS
SIGNAL BR:STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL SR:STD_LOGIC_VECTOR(7 DOWNTO 0):="10000000";
SIGNAL COUNT:STD_LOGIC_VECTOR(2 DOWNTO 0):="000";
BEGIN
PROCESS(CLK,EN,RW,RDY,BR,SR)
BEGIN
IF EN='1' THEN
IF CLK'EVENT AND CLK='1' THEN
IF RW='1' THEN
COUNT<=COUNT+1;
PD<=BR;
IF RDY='1' THEN
TR<='1';
ELSIF RDY='0' THEN
TR<='0';
END IF;
ELSIF RW='0' THEN
COUNT<=COUNT+1;
PD<=X"00";
IF SR(7)='1' AND SR(0)='0' THEN
SR(7)<='0';
BR<=DIN;
END IF;
END IF;
IF COUNT="101" THEN
SR(7)<='1';
COUNT<="000";
END IF;
END IF;
ELSIF EN='0' THEN
COUNT<="000";
BR<=X"00";
SR<=X"80";
END IF;
END PROCESS;
END BEHAVE;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PRINTER IS
PORT ( CLK: IN STD_LOGIC;
RESET: IN STD_LOGIC;
TR: IN STD_LOGIC;
PD: IN STD_LOGIC_VECTOR(7 DOWNTO 0);
RDY: OUT STD_LOGIC;
PDOUT: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
END PRINTER;
ARCHITECTURE BEHAVE OF PRINTER IS
SIGNAL COUNT:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
PROCESS(CLK,RESET,COUNT,TR,PD)
BEGIN
IF RESET='0' THEN
IF CLK'EVENT AND CLK='1' THEN
COUNT<=COUNT+1;
IF TR='1' THEN
COUNT<="000";
RDY<='0';
PDOUT<=PD;
ELSIF COUNT="101" THEN
RDY<='1';
COUNT<="000";
END IF;
END IF;
ELSIF RESET='1' THEN
RDY<='1';
END IF;
END PROCESS;
END BEHAVE;
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