prev_cmp_traffic.qmsg

VHDL 学习很好的一个例程

{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" {  } {  } 0 0 "Assembler is generating device programming files" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "136 " "Info: Peak virtual memory: 136 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 20 17:25:50 2009 " "Info: Processing ended: Mon Apr 20 17:25:50 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Apr 20 17:25:51 2009 " "Info: Processing started: Mon Apr 20 17:25:51 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off traffic -c traffic " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off traffic -c traffic" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "traffic.vhd" "" { Text "C:/altera/80/quartus/vhdl/integratedexperiment/trafficlight/traffic/traffic.vhd" 12 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "div_cnt\[15\] " "Info: Detected ripple clock \"div_cnt\[15\]\" as buffer" {  } { { "traffic.vhd" "" { Text "C:/altera/80/quartus/vhdl/integratedexperiment/trafficlight/traffic/traffic.vhd" 40 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "div_cnt\[15\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0} { "Info" "ITAN_RIPPLE_CLK" "div_cnt\[24\] " "Info: Detected ripple clock \"div_cnt\[24\]\" as buffer" {  } { { "traffic.vhd" "" { Text "C:/altera/80/quartus/vhdl/integratedexperiment/trafficlight/traffic/traffic.vhd" 40 -1 0 } } { "c:/altera/80/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/80/quartus/bin/Assignment Editor.qase" 1 { { 0 "div_cnt\[24\]" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register first\[0\] register first\[0\] 129.53 MHz 7.72 ns Internal " "Info: Clock \"clk\" has Internal fmax of 129.53 MHz between source register \"first\[0\]\" and destination register \"first\[0\]\" (period= 7.72 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.011 ns + Longest register register " "Info: + Longest register to register delay is 7.011 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns first\[0\] 1 REG LC_X8_Y10_N5 7 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y10_N5; Fanout = 7; REG Node = 'first\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { first[0] } "NODE_NAME" } } { "traffic.vhd" "" { Text "C:/altera/80/quartus/vhdl/integratedexperiment/trafficlight/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.084 ns) + CELL(0.200 ns) 2.284 ns Equal0~31 2 COMB LC_X8_Y10_N3 6 " "Info: 2: + IC(2.084 ns) + CELL(0.200 ns) = 2.284 ns; Loc. = LC_X8_Y10_N3; Fanout = 6; COMB Node = 'Equal0~31'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.284 ns" { first[0] Equal0~31 } "NODE_NAME" } } { "c:/altera/80/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "c:/altera/80/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1871 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.728 ns) + CELL(0.914 ns) 3.926 ns first\[3\]~377 3 COMB LC_X8_Y10_N4 4 " "Info: 3: + IC(0.728 ns) + CELL(0.914 ns) = 3.926 ns; Loc. = LC_X8_Y10_N4; Fanout = 4; COMB Node = 'first\[3\]~377'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.642 ns" { Equal0~31 first[3]~377 } "NODE_NAME" } } { "traffic.vhd" "" { Text "C:/altera/80/quartus/vhdl/integratedexperiment/trafficlight/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.177 ns) + CELL(1.908 ns) 7.011 ns first\[0\] 4 REG LC_X8_Y10_N5 7 " "Info: 4: + IC(1.177 ns) + CELL(1.908 ns) = 7.011 ns; Loc. = LC_X8_Y10_N5; Fanout = 7; REG Node = 'first\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "3.085 ns" { first[3]~377 first[0] } "NODE_NAME" } } { "traffic.vhd" "" { Text "C:/altera/80/quartus/vhdl/integratedexperiment/trafficlight/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.022 ns ( 43.10 % ) " "Info: Total cell delay = 3.022 ns ( 43.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.989 ns ( 56.90 % ) " "Info: Total interconnect delay = 3.989 ns ( 56.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.011 ns" { first[0] Equal0~31 first[3]~377 first[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.011 ns" { first[0] {} Equal0~31 {} first[3]~377 {} first[0] {} } { 0.000ns 2.084ns 0.728ns 1.177ns } { 0.000ns 0.200ns 0.914ns 1.908ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 12.213 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 12.213 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 25 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 25; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "traffic.vhd" "" { Text "C:/altera/80/quartus/vhdl/integratedexperiment/trafficlight/traffic/traffic.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.273 ns) + CELL(1.294 ns) 7.699 ns div_cnt\[24\] 2 REG LC_X14_Y3_N6 11 " "Info: 2: + IC(5.273 ns) + CELL(1.294 ns) = 7.699 ns; Loc. = LC_X14_Y3_N6; Fanout = 11; REG Node = 'div_cnt\[24\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.567 ns" { clk div_cnt[24] } "NODE_NAME" } } { "traffic.vhd" "" { Text "C:/altera/80/quartus/vhdl/integratedexperiment/trafficlight/traffic/traffic.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.596 ns) + CELL(0.918 ns) 12.213 ns first\[0\] 3 REG LC_X8_Y10_N5 7 " "Info: 3: + IC(3.596 ns) + CELL(0.918 ns) = 12.213 ns; Loc. = LC_X8_Y10_N5; Fanout = 7; REG Node = 'first\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.514 ns" { div_cnt[24] first[0] } "NODE_NAME" } } { "traffic.vhd" "" { Text "C:/altera/80/quartus/vhdl/integratedexperiment/trafficlight/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.344 ns ( 27.38 % ) " "Info: Total cell delay = 3.344 ns ( 27.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.869 ns ( 72.62 % ) " "Info: Total interconnect delay = 8.869 ns ( 72.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "12.213 ns" { clk div_cnt[24] first[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "12.213 ns" { clk {} clk~combout {} div_cnt[24] {} first[0] {} } { 0.000ns 0.000ns 5.273ns 3.596ns } { 0.000ns 1.132ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.213 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 12.213 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 25 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 25; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "traffic.vhd" "" { Text "C:/altera/80/quartus/vhdl/integratedexperiment/trafficlight/traffic/traffic.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.273 ns) + CELL(1.294 ns) 7.699 ns div_cnt\[24\] 2 REG LC_X14_Y3_N6 11 " "Info: 2: + IC(5.273 ns) + CELL(1.294 ns) = 7.699 ns; Loc. = LC_X14_Y3_N6; Fanout = 11; REG Node = 'div_cnt\[24\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.567 ns" { clk div_cnt[24] } "NODE_NAME" } } { "traffic.vhd" "" { Text "C:/altera/80/quartus/vhdl/integratedexperiment/trafficlight/traffic/traffic.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.596 ns) + CELL(0.918 ns) 12.213 ns first\[0\] 3 REG LC_X8_Y10_N5 7 " "Info: 3: + IC(3.596 ns) + CELL(0.918 ns) = 12.213 ns; Loc. = LC_X8_Y10_N5; Fanout = 7; REG Node = 'first\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.514 ns" { div_cnt[24] first[0] } "NODE_NAME" } } { "traffic.vhd" "" { Text "C:/altera/80/quartus/vhdl/integratedexperiment/trafficlight/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.344 ns ( 27.38 % ) " "Info: Total cell delay = 3.344 ns ( 27.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.869 ns ( 72.62 % ) " "Info: Total interconnect delay = 8.869 ns ( 72.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "12.213 ns" { clk div_cnt[24] first[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "12.213 ns" { clk {} clk~combout {} div_cnt[24] {} first[0] {} } { 0.000ns 0.000ns 5.273ns 3.596ns } { 0.000ns 1.132ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "12.213 ns" { clk div_cnt[24] first[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "12.213 ns" { clk {} clk~combout {} div_cnt[24] {} first[0] {} } { 0.000ns 0.000ns 5.273ns 3.596ns } { 0.000ns 1.132ns 1.294ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "traffic.vhd" "" { Text "C:/altera/80/quartus/vhdl/integratedexperiment/trafficlight/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "traffic.vhd" "" { Text "C:/altera/80/quartus/vhdl/integratedexperiment/trafficlight/traffic/traffic.vhd" 55 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "7.011 ns" { first[0] Equal0~31 first[3]~377 first[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "7.011 ns" { first[0] {} Equal0~31 {} first[3]~377 {} first[0] {} } { 0.000ns 2.084ns 0.728ns 1.177ns } { 0.000ns 0.200ns 0.914ns 1.908ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "12.213 ns" { clk div_cnt[24] first[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "12.213 ns" { clk {} clk~combout {} div_cnt[24] {} first[0] {} } { 0.000ns 0.000ns 5.273ns 3.596ns } { 0.000ns 1.132ns 1.294ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk dataout\[7\] en_xhdl\[0\] 21.846 ns register " "Info: tco from clock \"clk\" to destination pin \"dataout\[7\]\" through register \"en_xhdl\[0\]\" is 21.846 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 12.133 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 12.133 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns clk 1 CLK PIN_127 25 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_127; Fanout = 25; CLK Node = 'clk'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "traffic.vhd" "" { Text "C:/altera/80/quartus/vhdl/integratedexperiment/trafficlight/traffic/traffic.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.273 ns) + CELL(1.294 ns) 7.699 ns div_cnt\[15\] 2 REG LC_X13_Y3_N7 5 " "Info: 2: + IC(5.273 ns) + CELL(1.294 ns) = 7.699 ns; Loc. = LC_X13_Y3_N7; Fanout = 5; REG Node = 'div_cnt\[15\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "6.567 ns" { clk div_cnt[15] } "NODE_NAME" } } { "traffic.vhd" "" { Text "C:/altera/80/quartus/vhdl/integratedexperiment/trafficlight/traffic/traffic.vhd" 40 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.516 ns) + CELL(0.918 ns) 12.133 ns en_xhdl\[0\] 3 REG LC_X9_Y10_N7 6 " "Info: 3: + IC(3.516 ns) + CELL(0.918 ns) = 12.133 ns; Loc. = LC_X9_Y10_N7; Fanout = 6; REG Node = 'en_xhdl\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "4.434 ns" { div_cnt[15] en_xhdl[0] } "NODE_NAME" } } { "traffic.vhd" "" { Text "C:/altera/80/quartus/vhdl/integratedexperiment/trafficlight/traffic/traffic.vhd" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.344 ns ( 27.56 % ) " "Info: Total cell delay = 3.344 ns ( 27.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "8.789 ns ( 72.44 % ) " "Info: Total interconnect delay = 8.789 ns ( 72.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "12.133 ns" { clk div_cnt[15] en_xhdl[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "12.133 ns" { clk {} clk~combout {} div_cnt[15] {} en_xhdl[0] {} } { 0.000ns 0.000ns 5.273ns 3.516ns } { 0.000ns 1.132ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "traffic.vhd" "" { Text "C:/altera/80/quartus/vhdl/integratedexperiment/trafficlight/traffic/traffic.vhd" 130 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.337 ns + Longest register pin " "Info: + Longest register to pin delay is 9.337 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns en_xhdl\[0\] 1 REG LC_X9_Y10_N7 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X9_Y10_N7; Fanout = 6; REG Node = 'en_xhdl\[0\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "" { en_xhdl[0] } "NODE_NAME" } } { "traffic.vhd" "" { Text "C:/altera/80/quartus/vhdl/integratedexperiment/trafficlight/traffic/traffic.vhd" 130 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.452 ns) + CELL(0.914 ns) 2.366 ns data4\[1\]~165 2 COMB LC_X9_Y10_N1 7 " "Info: 2: + IC(1.452 ns) + CELL(0.914 ns) = 2.366 ns; Loc. = LC_X9_Y10_N1; Fanout = 7; COMB Node = 'data4\[1\]~165'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "2.366 ns" { en_xhdl[0] data4[1]~165 } "NODE_NAME" } } { "traffic.vhd" "" { Text "C:/altera/80/quartus/vhdl/integratedexperiment/trafficlight/traffic/traffic.vhd" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.201 ns) + CELL(0.511 ns) 4.078 ns Mux22~13 3 COMB LC_X9_Y10_N2 1 " "Info: 3: + IC(1.201 ns) + CELL(0.511 ns) = 4.078 ns; Loc. = LC_X9_Y10_N2; Fanout = 1; COMB Node = 'Mux22~13'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "1.712 ns" { data4[1]~165 Mux22~13 } "NODE_NAME" } } { "traffic.vhd" "" { Text "C:/altera/80/quartus/vhdl/integratedexperiment/trafficlight/traffic/traffic.vhd" 149 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.937 ns) + CELL(2.322 ns) 9.337 ns dataout\[7\] 4 PIN PIN_109 0 " "Info: 4: + IC(2.937 ns) + CELL(2.322 ns) = 9.337 ns; Loc. = PIN_109; Fanout = 0; PIN Node = 'dataout\[7\]'" {  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "5.259 ns" { Mux22~13 dataout[7] } "NODE_NAME" } } { "traffic.vhd" "" { Text "C:/altera/80/quartus/vhdl/integratedexperiment/trafficlight/traffic/traffic.vhd" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.747 ns ( 40.13 % ) " "Info: Total cell delay = 3.747 ns ( 40.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.590 ns ( 59.87 % ) " "Info: Total interconnect delay = 5.590 ns ( 59.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "9.337 ns" { en_xhdl[0] data4[1]~165 Mux22~13 dataout[7] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "9.337 ns" { en_xhdl[0] {} data4[1]~165 {} Mux22~13 {} dataout[7] {} } { 0.000ns 1.452ns 1.201ns 2.937ns } { 0.000ns 0.914ns 0.511ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "12.133 ns" { clk div_cnt[15] en_xhdl[0] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "12.133 ns" { clk {} clk~combout {} div_cnt[15] {} en_xhdl[0] {} } { 0.000ns 0.000ns 5.273ns 3.516ns } { 0.000ns 1.132ns 1.294ns 0.918ns } "" } } { "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/80/quartus/bin/TimingClosureFloorplan.fld" "" "9.337 ns" { en_xhdl[0] data4[1]~165 Mux22~13 dataout[7] } "NODE_NAME" } } { "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/80/quartus/bin/Technology_Viewer.qrui" "9.337 ns" { en_xhdl[0] {} data4[1]~165 {} Mux22~13 {} dataout[7] {} } { 0.000ns 1.452ns 1.201ns 2.937ns } { 0.000ns 0.914ns 0.511ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "121 " "Info: Peak virtual memory: 121 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Mon Apr 20 17:25:52 2009 " "Info: Processing ended: Mon Apr 20 17:25:52 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 5 s " "Info: Quartus II Full Compilation was successful. 0 errors, 5 warnings" {  } {  } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}