pc_io.v

采用Verilog语言实现了8255A的功能

          
//////////////////////////////////////////////////////////////////////////
//////////////////////////////内部联络信号寄存器//////////////////////////
//////////////////////////////////////////////////////////////////////////
  
  //-----INTEA_In-----
  always @ (reset or Flag or PortC_Out_Ld[4] or PortC_RS)
    if(reset)
      	INTEA_In = 1'b0;                                    //复位清0;
    else if(Flag==1'b0 && PortC_Out_Ld[4]==1'b0)
      	INTEA_In = PortC_RS;                                //由PC4置位复位决定;
    else                                                     
        INTEA_In = INTEA_In;                                //否则锁存原值;
  
  //-----INTEA_Out-----      
  always @ (reset or Flag or PortC_Out_Ld[6] or PortC_RS)
    if(reset)
      	INTEA_Out = 1'b0;                                   //复位清0;
    else if(Flag==1'b0 && PortC_Out_Ld[6]==1'b0)
      	INTEA_Out = PortC_RS;                               //由PC6置位复位决定
    else                                                    
        INTEA_Out = INTEA_Out;                              //否则锁存原值;
  
   //-----INTEB----- 
   always @ (reset or Flag or PortC_Out_Ld[2] or PortC_RS)
    if(reset)
      	INTEB = 1'b0;                                       //复位清0;
    else if(Flag==1'b0 && PortC_Out_Ld[2]==1'b0)
      	INTEB = PortC_RS;                                   //由PC6置位复位决定;
    else
        INTEB = INTEB;                                      //否则锁存原值;
        
  //-----nOBFA-----
  //-----nWR上升沿将其复位,nACKA将其置位,默认为高电平; 
  always @ (reset or ModeA or PortA_IO or nWR or nACKA or A or nSTBA)
     if(reset)
                        nOBFAstate=2'd0;
     else
       case(nOBFAstate)
         2'd0:   if(ModeA!=2'b00 && PortA_IO==1'b1 && nWR==1'b0)
                        nOBFAstate=2'd1;
                 else   nOBFAstate=2'd0;
                   
         2'd1:   if(nWR==1'b1 && A==2'b00)   
                        nOBFAstate=2'd2;
                 else   nOBFAstate=2'd1;
                   
         2'd2:   if(nACKA==1'b0)                            //nWR上升沿;
                        nOBFAstate=2'd0;
                 else   nOBFAstate=2'd2;
                   
       default:         nOBFAstate=2'd0;
       endcase
       
  always @ (nOBFAstate)
    if(nOBFAstate==2'd2)                                    //nWR上升沿情况;
      nOBFA=1'b0;
    else
      nOBFA=1'b1;            
 
  //-----nOBFB-----
  //-----nWR上升沿将其复位,nACKB将其置位,默认为高电平; 
  always @ (reset or ModeB or PortB_IO or nWR or nACKB or A)
     if(reset)
                        nOBFBstate=2'd0;
     else
       case(nOBFBstate)
         2'd0:   if(ModeB==1'b1 && PortB_IO==1'b1 && nWR==1'b0)
                        nOBFBstate=2'd1;
                 else   nOBFBstate=2'd0;
                   
         2'd1:   if(nWR==1'b1 && A==2'b01)    
                        nOBFBstate=2'd2;
                 else   nOBFBstate=2'd1;
                   
         2'd2:   if(ModeB==2'b01 && nACKB==1'b0)
                        nOBFBstate=2'd0;
                 else   nOBFBstate=2'd2;
                   
       default:         nOBFBstate=2'd0;
       endcase
       
  always @ (nOBFBstate)
    if(nOBFBstate==2'd2)
      nOBFB=1'b0;
    else
      nOBFB=1'b1;             
 
  //-----INTRA_In-----
  //-----nSTBA,IBFA,都为高时置位,nRD下降沿复位;
  always @ (reset or ModeA or PortA_IO or nSTBA or IBFA or nRD)
    if(reset)
                      INTRA_Instate=2'd0;
    else
      case(INTRA_Instate)
        2'd0:    if(ModeA!=2'b00 && nSTBA==1'b1 && IBFA==1'b1)
                      INTRA_Instate=2'd1;
                 else INTRA_Instate=2'd0;
        
        2'd1:    if(nRD==1'b0) 
                      INTRA_Instate=2'd2;
                 else INTRA_Instate=2'd1;
        2'd2:    if(nRD==1'b1)
                      INTRA_Instate=2'd0;
                 else INTRA_Instate=2'd2;
                 
        default:      INTRA_Instate=2'd0;
      endcase    
      
  always @ (INTRA_Instate)
    if(INTRA_Instate==2'd1 || INTRA_Instate==2'd2)
      INTRA_In=1'b1; 
    else
      INTRA_In=1'b0; 
 
  //-----INTRB_In-----
  //-----nSTBB,IBFB,都为高时置位,nRD下降沿复位;
  always @ (reset or ModeB or PortB_IO or nSTBB or IBFB or nRD)
    if(reset)
                      INTRB_Instate=2'd0;
    else
      case(INTRB_Instate)
        2'd0:    if(ModeB==2'b01 && nSTBB==1'b1 && IBFB==1'b1)
                      INTRB_Instate=2'd1;
                 else INTRB_Instate=2'd0;
        
        2'd1:    if(nRD==1'b0) 
                      INTRB_Instate=2'd2;
                 else INTRB_Instate=2'd1;
        2'd2:    if(nRD==1'b1)
                      INTRB_Instate=2'd0;
                 else INTRB_Instate=2'd2;
                 
        default:      INTRB_Instate=2'd0;
      endcase    
       
  always @ (INTRB_Instate)
    if(INTRB_Instate==2'd1 || INTRB_Instate==2'd2)
      INTRB_In=1'b1; 
    else
      INTRB_In=1'b0;
 
  //-----INTRA_Out-----
  //-----nACKA,nOBFA,都为高时置位,nWR下降沿复位;
  always @ (reset or ModeA or PortA_IO or nACKA or nOBFA or nWR)
    if(reset)
                       INTRA_Outstate=2'd0;
    else
      case(INTRA_Outstate)
        2'd0:   if(ModeA!=2'b00 && PortA_IO==1'b1 && nACKA==1'b1 && nOBFA==1'b1) 
                       INTRA_Outstate=2'd1;
                else   INTRA_Outstate=2'd0;
        2'd1:   if(nWR==1'b0) 
                       INTRA_Outstate=2'd2;
                else   INTRA_Outstate=2'd1;
                     
        2'd2:   if(nWR==1'b1)
                       INTRA_Outstate=2'd3;
                else if(PortA_IO==1'b0)
                       INTRA_Outstate=2'd0;
                else   INTRA_Outstate=2'd2;
                
        2'd3:   if(ModeA!=2'b00 && PortA_IO==1'b1 && nACKA==1'b1 && nOBFA==1'b1)
                       INTRA_Outstate=2'd1;
                else if(PortA_IO==1'b0)
                       INTRA_Outstate=2'd0;
                else   INTRA_Outstate=2'd3;                             
        default:       INTRA_Outstate=2'd0;
      endcase    
       
  always @ (INTRA_Outstate)
    if(INTRA_Outstate==2'd3)
      INTRA_Out=1'b0; 
    else
      INTRA_Out=1'b1; 
 
  //-----INTRB_Out-----
  //-----nACKB,nOBFB,都为高时置位,nWR下降沿复位;
  always @ (reset or ModeB or PortB_IO or nACKB or nOBFB or nWR)
    if(reset)
                       INTRB_Outstate=2'd0;
    else
      case(INTRB_Outstate)
        2'd0:    if(ModeB==2'b01 && PortB_IO==1'b1 && nACKB==1'b1 && nOBFB==1'b1)
                       INTRB_Outstate=2'd1;
                 else  INTRB_Outstate=2'd0;
        
        2'd1:    if(nWR==1'b0) 
                       INTRB_Outstate=2'd2;
                 else if(PortB_IO==1'b0)
                       INTRB_Outstate=2'd0;
                 else  INTRB_Outstate=2'd1;
                 
        2'd2:    if(nACKB==1'b0)
                       INTRB_Outstate=2'd3;
                 else if(PortB_IO==1'b0)
                       INTRB_Outstate=2'd0;
                 else  INTRB_Outstate=2'd2;                
        2'd3:    if(nACKB==1'b1)
                       INTRB_Outstate=2'd0;
                 else  INTRB_Outstate=2'd3;
                 
        default:       INTRB_Outstate=2'd0;               
      endcase    
       
  always @ (INTRB_Outstate)
    if(INTRB_Outstate==2'd2 || INTRB_Outstate==2'd3)
      INTRB_Out=1'b0; 
    else
      INTRB_Out=1'b1;     
         
  //-----IBFA-----
  //-----由nSTBA信号置位,由nRD上升沿复位;       
  always @ (reset or ModeA or PortA_IO or nSTBA or nRD)
    if(reset)
                       IBFAstate=2'd0;
    else
      case(IBFAstate)
        2'd0:    if(ModeA!=2'b00 && PortA_IO==1'b0 && nSTBA==1'b0)
                       IBFAstate=2'd1;
                 else  IBFAstate=2'd0;
        
        2'd1:    if(nRD==1'b0) 
                       IBFAstate=2'd2;
                 else  IBFAstate=2'd1;
        2'd2:    if(nRD==1'b1)
                       IBFAstate=2'd0;
                 else  IBFAstate=2'd2;
                 
        default:       IBFAstate=2'd0;
      endcase
      
  always @ (IBFAstate)
    if(IBFAstate==2'd1 || IBFAstate==2'd2)
      IBFA = 1'b1;
    else
      IBFA = 1'b0;       
                
  //-----IBFB-----
  //-----由nSTBB信号置位,由nRD上升沿复位;              
  always @ (reset or ModeB or PortB_IO or nSTBB or nRD)
    if(reset)
                       IBFBstate=2'd0;
    else
      case(IBFBstate)
        2'd0:    if(ModeB==2'b01 && PortB_IO==1'b0 && nSTBB==1'b0)
                       IBFBstate=2'd1;
                 else  IBFBstate=2'd0;
        
        2'd1:    if(nRD==1'b0) 
                       IBFBstate=2'd2;
                 else  IBFBstate=2'd1;
        2'd2:    if(nRD==1'b1)
                       IBFBstate=2'd0;
                 else  IBFBstate=2'd2;
                 
        default:       IBFBstate=2'd0;
      endcase
      
  always @ (IBFBstate)
    if(IBFBstate==2'd1 || IBFBstate==2'd2)
      IBFB = 1'b1;
    else
      IBFB = 1'b0;        
          
endmodule