txmit.v

异步串口发送模块

module txmit (reset,clock,data_in,write_strobe,s_out,transmiting);
output  s_out,transmiting;
input   [7:0] data_in;
input    reset,clock,write_strobe;
parameter baud_cnt=16;//代表波特率输入数据,数字代表接收时钟的分频数
reg     transmiting,txclk_enable,s_out,write_strobe1,write_strobe2;
reg     [7:0] tsr,tbr;
reg     [3:0] clkdiv,control_cnt;
reg    txclk;
wire    [7:0] data_in;
/*写入控制信号寄存器,用于下降沿检测*/
always @ (posedge clock)
        begin  write_strobe1<=write_strobe;
               write_strobe2<=write_strobe1; 
        end
/*发送时钟使能,在时钟使能范围内产生发送时钟,发送数据与此时钟同步*/
always @ (posedge clock or posedge reset)
        begin  if (reset)
                  begin transmiting<=1'b0;
                        txclk_enable<=1'b0;
                  end
            else if (!write_strobe1 && write_strobe2) //检测下降沿  
                  begin   txclk_enable<=1'b1;  end
            else if (control_cnt==2)                          
                  begin   transmiting<=1'b1;  end
            else if (control_cnt==12)                          
                  begin   txclk_enable<=1'b0; 
                          transmiting<=1'b0;  end
        end
/*控制计数器*/
always @ (posedge txclk or posedge reset or negedge txclk_enable )
          if (reset)    control_cnt<=0;
       else if (!txclk_enable)   control_cnt<=0;
           else  control_cnt<=control_cnt+1; 
/*在write_strobe的下降沿接收并行数据到发送缓冲寄存器*/   
always @ (negedge write_strobe or posedge reset)
        begin if (reset)  tbr<=8'b0;
               else       tbr<=data_in; 
        end
/*产生发送时钟*/
always @ (posedge clock or posedge reset)
        begin  if (reset)  clkdiv<=0;
               else begin 
                     if (txclk_enable)            
                         begin if (clkdiv>=(baud_cnt-1))
                                   clkdiv<=0;
                                else  clkdiv<=clkdiv+1;
                          end
                    end
        end
    //assign txclk = (clkdiv>=(baud_cnt-1))? 1 : 0;
always @ (posedge clock or posedge reset )
       begin  if (reset) txclk<=0;
              else if(clkdiv>=baud_cnt-1) txclk<=1;
                   else txclk<=0;
       end
always @ (negedge txclk  or posedge reset)
         if (reset)  begin  s_out <=1'b1; 
                            tsr=8'b00000000; 
                     end
              else begin  if (control_cnt==1)  tsr<=tbr;
                     else if  (control_cnt==2) s_out <=1'b0;
                     else if  ((control_cnt>=3) && (control_cnt<=10))
                              begin  tsr[6:0]<= tsr[7:1];
                                       tsr[7]<= 1'b0; 
                                       s_out <= tsr[0];
                              end 
                     else if  (control_cnt==11) s_out <=1'b1;
                   end
endmodule