songer.tan.rpt

来自「简单的乐曲播放器,实验课程作品,使用VHDL语言编写」· RPT 代码 · 共 270 行 · 第 1/5 页

; Number of destination nodes to report                 ; 10                 ;      ;    ;
; Number of paths to report                             ; 200                ;      ;    ;
; Run Minimum Analysis                                  ; On                 ;      ;    ;
; Use Minimum Timing Models                             ; Off                ;      ;    ;
; Report IO Paths Separately                            ; Off                ;      ;    ;
; Clock Analysis Only                                   ; Off                ;      ;    ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;
; Cut off read during write signal paths                ; On                 ;      ;    ;
; Cut off clear and preset signal paths                 ; On                 ;      ;    ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;
+-------------------------------------------------------+--------------------+------+----+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                             ;
+------------------------------+-------+---------------+----------------------------------+------------------------+-----------------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack ; Required Time ; Actual Time                      ; From                   ; To                                                        ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+------------------------+-----------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A   ; None          ; 11.000 ns                        ; MODE                   ; NoteTabs:u1|Counter[6]                                    ;            ; CLK1MHZ  ; 0            ;
; Worst-case tco               ; N/A   ; None          ; 55.000 ns                        ; NoteTabs:u1|Counter[0] ; CAIDENG[6]                                                ; CLK1MHZ    ;          ; 0            ;
; Worst-case th                ; N/A   ; None          ; 6.000 ns                         ; NEXTONE                ; NoteTabs:u1|SHOW                                          ;            ; CLK1MHZ  ; 0            ;
; Worst-case Minimum tco       ; N/A   ; None          ; 17.000 ns                        ; NoteTabs:u1|SHOW       ; SHOW                                                      ; CLK1MHZ    ;          ; 0            ;
; Clock Setup: 'CLK1MHZ'       ; N/A   ; None          ; 17.24 MHz ( period = 58.000 ns ) ; NoteTabs:u1|Counter[0] ; Speakera:u3|lpm_counter:\GenSpks:Count11[0]_rtl_0|dffs[3] ; CLK1MHZ    ; CLK1MHZ  ; 0            ;
; Total number of failed paths ;       ;               ;                                  ;                        ;                                                           ;            ;          ; 0            ;
+------------------------------+-------+---------------+----------------------------------+------------------------+-----------------------------------------------------------+------------+----------+--------------+


+--------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                               ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+
; CLK1MHZ         ;                    ; User Pin ; NONE             ; NONE     ; N/A                   ; N/A                 ; N/A    ;
+-----------------+--------------------+----------+------------------+----------+-----------------------+---------------------+--------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK1MHZ'                                                                                                                                                                                                                                                                                                              ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                       ; To                                                         ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------------+------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 17.24 MHz ( period = 58.000 ns )                    ; NoteTabs:u1|Counter[7]                                     ; Speakera:u3|lpm_counter:\GenSpks:Count11[0]_rtl_0|dffs[5]  ; CLK1MHZ    ; CLK1MHZ  ; None                        ; None                      ; None                    ;
; N/A                                     ; 17.24 MHz ( period = 58.000 ns )                    ; NoteTabs:u1|Counter[6]                                     ; Speakera:u3|lpm_counter:\GenSpks:Count11[0]_rtl_0|dffs[5]  ; CLK1MHZ    ; CLK1MHZ  ; None                        ; None                      ; None                    ;
; N/A                                     ; 17.24 MHz ( period = 58.000 ns )                    ; NoteTabs:u1|Counter[5]                                     ; Speakera:u3|lpm_counter:\GenSpks:Count11[0]_rtl_0|dffs[5]  ; CLK1MHZ    ; CLK1MHZ  ; None                        ; None                      ; None                    ;
; N/A                                     ; 17.24 MHz ( period = 58.000 ns )                    ; NoteTabs:u1|Counter[4]                                     ; Speakera:u3|lpm_counter:\GenSpks:Count11[0]_rtl_0|dffs[5]  ; CLK1MHZ    ; CLK1MHZ  ; None                        ; None                      ; None                    ;
; N/A                                     ; 17.24 MHz ( period = 58.000 ns )                    ; NoteTabs:u1|Counter[3]                                     ; Speakera:u3|lpm_counter:\GenSpks:Count11[0]_rtl_0|dffs[5]  ; CLK1MHZ    ; CLK1MHZ  ; None                        ; None                      ; None                    ;
; N/A                                     ; 17.24 MHz ( period = 58.000 ns )                    ; NoteTabs:u1|Counter[2]                                     ; Speakera:u3|lpm_counter:\GenSpks:Count11[0]_rtl_0|dffs[5]  ; CLK1MHZ    ; CLK1MHZ  ; None                        ; None                      ; None                    ;
; N/A                                     ; 17.24 MHz ( period = 58.000 ns )                    ; NoteTabs:u1|Counter[1]                                     ; Speakera:u3|lpm_counter:\GenSpks:Count11[0]_rtl_0|dffs[5]  ; CLK1MHZ    ; CLK1MHZ  ; None                        ; None                      ; None                    ;
; N/A                                     ; 17.24 MHz ( period = 58.000 ns )                    ; NoteTabs:u1|Counter[0]                                     ; Speakera:u3|lpm_counter:\GenSpks:Count11[0]_rtl_0|dffs[5]  ; CLK1MHZ    ; CLK1MHZ  ; None                        ; None                      ; None                    ;
; N/A                                     ; 17.24 MHz ( period = 58.000 ns )                    ; NoteTabs:u1|Counter[7]                                     ; Speakera:u3|lpm_counter:\GenSpks:Count11[0]_rtl_0|dffs[4]  ; CLK1MHZ    ; CLK1MHZ  ; None                        ; None                      ; None                    ;
; N/A                                     ; 17.24 MHz ( period = 58.000 ns )                    ; NoteTabs:u1|Counter[6]                                     ; Speakera:u3|lpm_counter:\GenSpks:Count11[0]_rtl_0|dffs[4]  ; CLK1MHZ    ; CLK1MHZ  ; None                        ; None                      ; None                    ;