songer.map.rpt

简单的乐曲播放器,实验课程作品,使用VHDL语言编写

+-----------------------------------------------+------------+------+------------------------------------------------------------------------------------+
; Compilation Hierarchy Node                    ; Macrocells ; Pins ; Full Hierarchy Name                                                                ;
+-----------------------------------------------+------------+------+------------------------------------------------------------------------------------+
; |Songer                                       ; 127        ; 28   ; |Songer                                                                            ;
;    |NoteTabs:u1|                              ; 40         ; 0    ; |Songer|NoteTabs:u1                                                                ;
;       |lpm_add_sub:add_rtl_1|                 ; 1          ; 0    ; |Songer|NoteTabs:u1|lpm_add_sub:add_rtl_1                                          ;
;          |addcore:adder[0]|                   ; 1          ; 0    ; |Songer|NoteTabs:u1|lpm_add_sub:add_rtl_1|addcore:adder[0]                         ;
;             |a_csnbuffer:result_node|         ; 1          ; 0    ; |Songer|NoteTabs:u1|lpm_add_sub:add_rtl_1|addcore:adder[0]|a_csnbuffer:result_node ;
;    |Speakera:u3|                              ; 33         ; 0    ; |Songer|Speakera:u3                                                                ;
;       |lpm_counter:\GenSpks:Count11[0]_rtl_0| ; 16         ; 0    ; |Songer|Speakera:u3|lpm_counter:\GenSpks:Count11[0]_rtl_0                          ;
;    |ToneTaba:u2|                              ; 18         ; 0    ; |Songer|ToneTaba:u2                                                                ;
;    |lpm_add_sub:add_rtl_2|                    ; 1          ; 0    ; |Songer|lpm_add_sub:add_rtl_2                                                      ;
;       |addcore:adder[1]|                      ; 1          ; 0    ; |Songer|lpm_add_sub:add_rtl_2|addcore:adder[1]                                     ;
+-----------------------------------------------+------------+------+------------------------------------------------------------------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/乐曲播放器/乐曲播放器(最终上传）/Songer.map.eqn.


+--------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                         ;
+--------------------------------------------------------------+-----------------+
; File Name                                                    ; Used in Netlist ;
+--------------------------------------------------------------+-----------------+
; NoteTabs.vhd                                                 ; yes             ;
; Songer.vhd                                                   ; yes             ;
; Speakera.vhd                                                 ; yes             ;
; ToneTaba.vhd                                                 ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf  ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/lpm_constant.inc ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf  ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/addcore.inc      ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/look_add.inc     ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/addcore.tdf      ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf  ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/look_add.tdf     ; yes             ;
; c:/altera/quartus41/libraries/megafunctions/altshift.tdf     ; yes             ;
+--------------------------------------------------------------+-----------------+


+-----------------------------------------------+
; Analysis & Synthesis Resource Usage Summary   ;
+----------------------+------------------------+
; Resource             ; Usage                  ;
+----------------------+------------------------+
; Logic cells          ; 127                    ;
; Total registers      ; 51                     ;
; I/O pins             ; 28                     ;
; Shareable expanders  ; 48                     ;
; Parallel expanders   ; 26                     ;
; Maximum fan-out node ; NoteTabs:u1|Counter[3] ;
; Maximum fan-out      ; 59                     ;
; Total fan-out        ; 1326                   ;
; Average fan-out      ; 6.53                   ;
+----------------------+------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 4.1 Build 181 06/29/2004 SJ Full Version
    Info: Processing started: Wed Oct 17 13:17:22 2007
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off Songer -c Songer
Info: Found 2 design units, including 1 entities, in source file NoteTabs.vhd
    Info: Found design unit 1: NoteTabs-one
    Info: Found entity 1: NoteTabs
Info: Found 2 design units, including 1 entities, in source file Songer.vhd
    Info: Found design unit 1: Songer-one
    Info: Found entity 1: Songer
Info: Found 2 design units, including 1 entities, in source file Speakera.vhd
    Info: Found design unit 1: Speakera-one
    Info: Found entity 1: Speakera
Info: Found 2 design units, including 1 entities, in source file ToneTaba.vhd
    Info: Found design unit 1: ToneTaba-one
    Info: Found entity 1: ToneTaba
Warning: VHDL Process Statement warning at NoteTabs.vhd(68): signal counter is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at NoteTabs.vhd(69): signal counter is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at NoteTabs.vhd(70): signal counter is in statement, but is not in sensitivity list
Warning: VHDL Process Statement warning at NoteTabs.vhd(66): signal or variable seg may not be assigned a new value in every possible path through the Process Statement. Signal or variable seg holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: VHDL Case Statement information at NoteTabs.vhd(327): OTHERS choice is never selected
Info: VHDL Case Statement information at ToneTaba.vhd(33): OTHERS choice is never selected
Warning: VHDL Process Statement warning at ToneTaba.vhd(14): signal or variable caideng may not be assigned a new value in every possible path through the Process Statement. Signal or variable caideng holds its previous value in every path with no new value assignment, which may create a combinational loop in the current design.
Info: Inferred 1 megafunctions from design logic
    Info: Inferred lpm_counter megafunction (LPM_WIDTH=11) from the following logic: Speakera:u3|\GenSpks:Count11[0]~0
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/lpm_counter.tdf
    Info: Found entity 1: lpm_counter
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/lpm_add_sub.tdf
    Info: Found entity 1: lpm_add_sub
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/addcore.tdf
    Info: Found entity 1: addcore
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/a_csnbuffer.tdf
    Info: Found entity 1: a_csnbuffer
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/look_add.tdf
    Info: Found entity 1: look_add
Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus41/libraries/megafunctions/altshift.tdf
    Info: Found entity 1: altshift
Info: Ignored 24 buffer(s)
    Info: Ignored 24 SOFT buffer(s)
Info: Duplicate registers merged to single register
    Info: Duplicate register Speakera:u3|\DelaySpks:Count2 merged to single register Speakera:u3|Spks
Info: Registers with preset signals will power-up high
Warning: LATCH primitive NoteTabs:u1|SEG[0] is permanently enabled
Warning: LATCH primitive NoteTabs:u1|SEG[5] is permanently enabled
Warning: LATCH primitive NoteTabs:u1|SEG[4] is permanently enabled
Warning: LATCH primitive NoteTabs:u1|SEG[2] is permanently enabled
Warning: LATCH primitive NoteTabs:u1|SEG[1] is permanently enabled
Warning: Output pins are stuck at VCC or GND
    Warning: Pin SEG[5] stuck at VCC
    Warning: Pin SEG[1] stuck at GND
    Warning: Pin CAT[5] stuck at GND
    Warning: Pin CAT[4] stuck at VCC
    Warning: Pin CAT[3] stuck at VCC
    Warning: Pin CAT[2] stuck at VCC
    Warning: Pin CAT[1] stuck at VCC
    Warning: Pin CAT[0] stuck at VCC
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin CLK1MHZ to global clock signal
Info: Promoted pin-driven signal(s) to global signal
    Info: Promoted clock signal driven by pin CLK1MHZ to global clock signal
Info: Implemented 203 device resources after synthesis - the final resource count might be different
    Info: Implemented 6 input pins
    Info: Implemented 22 output pins
    Info: Implemented 127 macrocells
    Info: Implemented 48 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 19 warnings
    Info: Processing ended: Wed Oct 17 13:18:06 2007
    Info: Elapsed time: 00:00:43