speakera.vhd

简单的乐曲播放器,实验课程作品,使用VHDL语言编写

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY Speakera IS
    PORT ( clk :IN STD_LOGIC;         --1MHz
           Tone : IN INTEGER RANGE 0 TO 16#7FF#;   --音调分频比率
           Spks :OUT STD_LOGIC  );      --频率输出给蜂鸣器
END;

ARCHITECTURE one OF Speakera IS
  SIGNAL PreCLK : STD_LOGIC;
  SIGNAL FullSpks : STD_LOGIC;
BEGIN
 DivideCLK : PROCESS(clk)                 --将1M 频率三分频
    VARIABLE Count4 : INTEGER RANGE 0 TO 2;
    BEGIN 
       PreCLK <= '0';
      IF Count4 =2 THEN  PreCLK <='1' ; Count4 := 0;
      ELSIF clk'EVENT AND clk='1'   THEN  Count4 := Count4+1;
      END IF ;
   END PROCESS;
  GenSpks : PROCESS (PreCLK,Tone)
       VARIABLE Count11 : INTEGER RANGE 0 TO 16#7FF#;
  BEGIN
        IF PreCLK'EVENT AND PreCLK='1'  THEN       --按分频比分频
           IF Count11 = Tone THEN
             Count11 :=0;
              FullSpks <='1';
         ELSE  Count11 := Count11 +1;
               FullSpks <='0';   END IF;
       END IF;
  END PROCESS;
  DelaySpks : PROCESS (FullSpks)        
      VARIABLE Count2 : STD_LOGIC;
BEGIN                                        
      IF FullSpks'EVENT AND FullSpks='1'  THEN         --D触发器2分频，保证蜂鸣器发声稳定
         Count2:= NOT Count2 ;
         IF Count2 ='1'   THEN Spks <='1';
          ELSE    Spks <='0';  END IF;
      END IF;
    END PROCESS;
END;