📄 outputmanager.v
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//******************************************************************************
//OutputManager - Module to output 5 bytes by using 1 byte output and
// chip select. Continuously refreshes the output.
// Used in conjunction with 74LS373 octal latches:
// - out - for input of each latch
// - cs - for enable of each chip
// See documentation for details. Should work with +ve or
// -ve edge triggered flip-flops as well. Tested and
// verified for 74LS373 octal latches (2005-12-26).
//
//******************************************************************************
module OutputManager(ShiftLevel, TriggerLevel, AmpLevel, out, cs, clk);
input [15:0] ShiftLevel;
input [15:0] TriggerLevel;
input [7:0] AmpLevel;
output [7:0] out;
output [4:0] cs;
input clk;
reg [7:0] out;
reg [3:0] ps, ns;
parameter A1 = 4'h0, //Chip 1 - Load data for output
B1 = 4'h1, // Send strobe for external latches
C1 = 4'h2, // Extra hold time
A2 = 4'h3, //Chip 2
B2 = 4'h4,
C2 = 4'h5,
A3 = 4'h6, //Chip 3
B3 = 4'h7,
C3 = 4'h8,
A4 = 4'h9, //Chip 4
B4 = 4'hA,
C4 = 4'hB,
A5 = 4'hC, //Chip 5
B5 = 4'hD,
C5 = 4'hE;
always @ (ps) begin
case (ps)
A1: ns = B1;
B1: ns = C1;
C1: ns = A2;
A2: ns = B2;
B2: ns = C2;
C2: ns = A3;
A3: ns = B3;
B3: ns = C3;
C3: ns = A4;
A4: ns = B4;
B4: ns = C4;
C4: ns = A5;
A5: ns = B5;
B5: ns = C5;
C5: ns = A1;
default: ns = A1;
endcase
end
always @ (posedge clk) begin
ps <= ns;
case (ns)
A1: out <= ShiftLevel[7:0];
A2: out <= ShiftLevel[15:8];
A3: out <= TriggerLevel[7:0];
A4: out <= TriggerLevel[15:8];
A5: out <= AmpLevel[7:0];
default: out <= out;
endcase
end
assign cs[0] = (ps == B1);
assign cs[1] = (ps == B2);
assign cs[2] = (ps == B3);
assign cs[3] = (ps == B4);
assign cs[4] = (ps == B5);
endmodule
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