oscilloscopeprototype.v

A prototype of Digital Oscilloscope

module OscilloscopePrototype(rx, tx, LED, clk,
		out, cs,
		ADCClk, ADCIn, /*ADCInt,*/ ADCWR,
		fn1Hz, fn10Hz, fn100Hz, fn1kHz);
	input	rx, clk;
	output	tx, LED;

	output	[7:0] out;
	output	[4:0] cs;

//	input	ADCInt;
	input	[7:0] ADCIn;
	output	ADCClk;
	output	ADCWR;
	reg		[7:0] ADCData;
	reg		ADCWR;

	output	fn1Hz, fn10Hz, fn100Hz, fn1kHz;
	reg		[14:0] Divide1kHz;
	reg		[3:0] Divide100Hz, Divide10Hz, Divide1Hz;

	wire	[63:0] StatReg;

	SerialRxManager SRxM(.rx(rx), .outdata(StatReg), .clk(clk));
	OutputManager OM(.ShiftLevel(StatReg[15:0]), .TriggerLevel(StatReg[31:16]),
			.AmpLevel(StatReg[39:32]), .out(out), .cs(cs), .clk(clk));

	//*************************************
	//Function generators (square waves)
	always @ (posedge clk) begin
		if (Divide1kHz == 15'd27000) begin
			Divide1kHz <= 15'd0;
		end else begin
			Divide1kHz <= Divide1kHz + 1'd1;
		end
	end
	assign fn1kHz = Divide1kHz[14];

	always @ (posedge Divide1kHz[14]) begin
		if (Divide100Hz == 4'd10) begin
			Divide100Hz <= 4'd0;
		end else begin
			Divide100Hz <= Divide100Hz + 1'd1;
		end
	end
	assign fn100Hz = Divide100Hz[3];

	always @ (posedge Divide100Hz[3]) begin
		if (Divide10Hz == 4'd10) begin
			Divide10Hz <= 4'd0;
		end else begin
			Divide10Hz <= Divide10Hz + 1'd1;
		end
	end
	assign fn10Hz = Divide10Hz[3];

	always @ (posedge Divide10Hz[3]) begin
		if (Divide1Hz == 4'd10) begin
			Divide1Hz <= 4'd0;
		end else begin
			Divide1Hz <= Divide1Hz + 1'd1;
		end
	end
	assign fn1Hz = Divide1Hz[3];
	//End of function generators
	//*************************************

	//*************************************
	//ADCClock generator
	reg	[5:0] ADCClkCtr;
	always @ (posedge clk) begin
		if (ADCClkCtr == 6'd43)	ADCClkCtr <= 0;
		else					ADCClkCtr <= ADCClkCtr + 1'b1;
	end
	assign ADCClk = ADCClkCtr[5];
	//End of ADCClock generator
	//*************************************

	//*************************************
	//Sampling clock
	reg	[11:0] SampleCtr;
	always @ (posedge clk) begin
		if (SampleCtr == 12'd3374)	SampleCtr <= 0;
		else						SampleCtr <= SampleCtr + 1'b1;
	end
	wire SampleClk = (SampleCtr == 12'd3374);
	//End of sampling clock
	//*************************************

	reg	[2:0] ps, ns;
	parameter	A = 3'h0,
				B = 3'h1,
				C = 3'h2,
				D = 3'h3,
				E = 3'h4,
				F = 3'h5;

	always @ (ps or SampleClk) begin
		case (ps)
			A:					ns = B;
			B:					ns = C;
			C:					ns = D;
			D:					ns = E;
			E:					ns = F;
			F:	if (SampleClk)	ns = A;
				else			ns = F;
			default:			ns = A;
		endcase
	end

	always @ (posedge clk or posedge StatReg[56]) begin
		if (StatReg[56]) begin
			ps <= A;
			ADCWR <= 1'b1;
		end else begin
			if (ps == B)	ADCData <= ADCIn;
			else			ADCData <= ADCData;
			case (ps)
				C:			ADCWR <= 1'b0;
				F:			ADCWR <= 1'b1;
				default:	ADCWR <= ADCWR;
			endcase
			ps <= ns;
		end
	end

	//Disable output if reset bit is set (ADCWR & ~StatReg[56])
	async_transmitter ATx(.clk(clk), .TxD_start(ADCWR & ~StatReg[56]),
			.TxD_data(ADCData), .TxD(tx));

	assign LED = ~(rx & tx);
//	assign LED = StatReg[56];
endmodule