fifo.v

A First in first out buffer in Verilog

// ============================================================
// File Name: fifo.v



module fifo (
	data,
	wrreq,
	rdreq,
	rdclk,
	wrclk,
	q,
	rdfull,
	rdempty,
	wrfull,
	wrempty);

	input	[7:0]  data;
	input	  wrreq;
	input	  rdreq;
	input	  rdclk;
	input	  wrclk;
	output	[7:0]  q;
	output	  rdfull;
	output	  rdempty;
	output	  wrfull;
	output	  wrempty;

	wire  sub_wire0;
	wire  sub_wire1;
	wire  sub_wire2;
	wire  sub_wire3;
	wire [7:0] sub_wire4;
	wire  rdfull = sub_wire0;
	wire  rdempty = sub_wire1;
	wire  wrfull = sub_wire2;
	wire  wrempty = sub_wire3;
	wire [7:0] q = sub_wire4[7:0];

	dcfifo	dcfifo_component (
				.wrclk (wrclk),
				.rdreq (rdreq),
				.rdclk (rdclk),
				.wrreq (wrreq),
				.data (data),
				.rdfull (sub_wire0),
				.rdempty (sub_wire1),
				.wrfull (sub_wire2),
				.wrempty (sub_wire3),
				.q (sub_wire4));
	defparam
		dcfifo_component.intended_device_family = "ACEX1K",
		dcfifo_component.lpm_width = 8,
		dcfifo_component.lpm_numwords = 1024,
		dcfifo_component.lpm_widthu = 10,
		dcfifo_component.clocks_are_synchronized = "FALSE",
		dcfifo_component.lpm_type = "dcfifo",
		dcfifo_component.lpm_showahead = "OFF",
		dcfifo_component.overflow_checking = "ON",
		dcfifo_component.underflow_checking = "ON",
		dcfifo_component.use_eab = "ON",
		dcfifo_component.lpm_hint = "";


endmodule