counta3d5.v.bak

FPGA的集成开发环境ISE中课仿真的Verilog代码集锦

module counta3d5(rst,clk,up,dn,din,dout,par,carry,borrow);
       input rst,clk,up,dn;
       input[7:0]din;
       output[7:0]dout;
       output par,carry,borrow;
       
       reg [7:0]dout;
       reg par,carry,borrow;
       
       reg[8:0]cnt_next;
       
       always@(up or dn or dout)
           case{{up,dn}}
           	   2'b00:cnt_next=din;
           	   2'b01:cnt_next=dout-3'b101;
           	   2'b10:cnt_next=dout+2'b11;
           	   2'b11:cnt_next=cnt_next;
           endcase
       always@(posedge clk or rst)begin
           if(!rst)begin
              dout<=0;
              par<=0;
              carry<=0;
              borrow<=0;
           end
          else begin
             par=^cnt_next;
             carry=up&&cnt_next[8];
             borrow=dn&&cnt_next[8];
             dout<=cnt_next;           
          end       
       end
      endmodule