tb_traffic_light_controller.v

来自「FPGA的集成开发环境ISE中课仿真的Verilog代码集锦」· Verilog 代码 · 共 25 行

//***************************************************
// File Name: tb_traffic_light_controller.v
//      Date: September 29,2008
//    author: yilong.you
//            [e-mail]   
//**************************************************/
`timescale 1ns/1ns
module tb_traffic_light_controller;
    reg clk,reset;
    wire[1:0] light_color;
    
    traffic_light_controller h1(.clk(clk),.reset(reset),.light_color(light_color));  
    always #1 clk=~clk;
    initial begin
       clk=0;      
       reset=1;
       #2 reset=0;
       #100$stop;    
    end
    always@(negedge clk)begin
       $display("At time %t:light_color=%b",$time,light_color);
 end
endmodule