countu3d5.v.bak

FPGA的集成开发环境ISE中课仿真的Verilog代码集锦

module countu3d5(rst, clk, up, dn, din, dout, par, carry, borrow);
 input rst, clk, up, dn;
 input [7:0] din;
 output [7:0] dout;
 output par, carry, borrow;
 reg [7:0] dout;
 reg par, carry, borrow;
 wire [8:0] cnt_up, cnt_dn;   
 reg [7:0] cnt_nxt;
      assign  cnt_dn = dout - 3'b101;  
      assign  cnt_up = dout + 2'b11;   
      always@(up or dn or din or cnt_dn or cnt_up)
         case ({up,dn})
               2'b 00 : cnt_nxt = din;
               2'b 01 : cnt_nxt = cnt_dn;
               2'b 10 : cnt_nxt = cnt_up;
               2'b 11 : cnt_nxt = cnt_nxt; 
         endcase

      always @(posedge clk or negedge rst)
      begin
        if(!rst) begin
            dout<=0;
            par<=0;
            carry<=0;
            borrow<=0;
        end
        else begin
            par <= ^cnt_nxt;
            carry <= up & cnt_up[8];
            borrow <= dn & cnt_dn[8];
            dout <= cnt_nxt;
        end
      end
endmodule
/*
always@(posedge clk or negedge rst)
begin
if(!rst) begin
  dout <= 0;
  par <= 0;
  carry <= 0;
  borrow <= 0;
end
else begin
case {up, dn}
2'b00: dout<=din;
2'b01: {carry, dout}<=dout + 2'b11;
2'b10: {borrow, dout}<=dout - 3'b101;
2'b11: dout<=dout;
endcase
par <= ^dout;
end
assign par = ^dout;
end
*/