multiply2.v.bak

FPGA的集成开发环境ISE中课仿真的Verilog代码集锦

module Multiply_tb;
	reg [15:0]Mplr,Mcnd;
	reg Clock,Reset;
	wire Done;
	wire[31:0]Acc;
	
	always #5 Clock=~Clock;
	initial begin
		Clock=0;
		Reset=0;
		#20 Reset=1;
		#20 Reset=0;
		repeat(5)begin
			#40 Mplr={$random}%65536;
			    Mcnd={$random}%65536
		
	   	$display("Mplr=%b---Mcnd=%b---Acc=%b",Mplr,Mcnd,Acc);
  	end
		#100000$stop;
	end
	
	Multiply c1(.Mplr(Mplr),.Mcnd(Mcnd),.Clock(Clock),.Reset(Reset),.Done(Done),.Acc(Acc));
endmodule