divider6_5.v.bak

FPGA的集成开发环境ISE中课仿真的Verilog代码集锦

//-----------------------------------------------------------
//  file name: N-5 divider
//     author: Yilong.you
//       date: October 14,2008
//----------------------------------------------------------

module dividerN.5(  clk_in  ,
                    reset   ,
                    clk_out  );//port list
       input     clk_in ;       
       input     reset  ;       
       output    clk_out;
       parameter N=6;
       wire clk_tmp;
       wire clk_rever;
       
       reg sel;
       reg[2:0]count;
       
       xor u1(clk_rever,1'b1,clk_in);
       
       initial sel=0;
       assign clk_tmp=sel?clk_rever:clk_in;
       
       always@(posedeg clk_tmp)begin
          if(reset)begin
             count<=0;
             clk_out<=0;
          end
          else begin
             if(count==N-1)begin
                sel<=1;
                count<=count+1;
             end
             
             else if(count==N)begin
                clk_out<=~clk_out;
                count<=count+1;  
             end
             
             else if(count==N+1)begin
                clk_out<=~clk_out;
                count<=1;
                sel<=0;
             end
          end 
       end
endmodule
         
`timescale 1ns/1ns
module tb_divider-5;
       reg   clk_in ;
       reg   reset  ;
       wire  clk_out;
       
       dividerN-5 c1(.clk_in(clk_in),.reset(reset),.clk_out(clk_out));
       
       always #1 clk_in=~clk_in;
       initial begin
       	    clk_in=0;
            reset =0;
         #2 reset =1;
         #2 reset =0;
         #100 $stop;     
       end      
endmodule