asynchronous_fsm.v.bak

FPGA的集成开发环境ISE中课仿真的Verilog代码集锦

module asynchronous_fsm(inputA,state);
    input inputA;
    output state;
    event state1,state2,state3;
    initial begin
       ->state1;
    end

    always@(state1)begin
       ->state2;
    end

    always@(state2)begin
       ->state3;
    end

    always@(state3)begin
       if(inputA) ->state2;
       else ->state1;
    end
  always@(state1)  state=state1;
  always@(state2)  state=state2;
  always@(state3)  state=state3;
endmodule