global_var.v.bak

来自「FPGA的集成开发环境ISE中课仿真的Verilog代码集锦」· BAK 代码 · 共 27 行

module Global_Var;
reg[0:7] RamQ[0:63];
integer index;
reg CheckBit;

initial
   begin
      for (index=0;index<=63;index=index+1)
         RamQ[index]={$random}%256; 
         index=index+1;     
   end
   
task GetParity;
   input Address;
   output ParityBit;
   ParityBit=^RamQ[Address];
endtask
   initial 
     for (index=0;index<=63;index=index+1)
     begin
        GetParity(index,CheckBit);
        $display("Parity bit of memory word %d is %b",index,CheckBit);
     end
 endmodule