traffic_light_controller.v.bak

来自「FPGA的集成开发环境ISE中课仿真的Verilog代码集锦」· BAK 代码 · 共 55 行

//***************************************************
// File Name: traffic_light_controller.v
//      Date: September 29,2008
//    author: yilong.you
//            [e-mail]   
//**************************************************/

module traffic_light_controller(clk,reset,light_color);
 input clk,reset;
 output[1:0] light_color; 

 reg[1:0] light_color,state;
 reg[5:0]count;
 
 parameter S0=2'd0,green=2'd1,yellow=2'd2,red=2'd3;
 
 initial state<=S0;
 always@(posedge clk or  posedge reset)begin
       if(reset)begin
            state<=S0;
            count<=0;
       end
       else begin
       	  if(count===0)
            state<=green;
         
          if(count==24)begin
            state<=yellow;
            count<=count+1;
          end
          
          else if(count==26)begin
            state<=red;
            count<=count+1;
          end
          
          else if(count==41)begin
            state<=green;
            count<=0;
          end 
          else count<=count+1;
       end
 end
 always@(negedge clk) light_color<=state;
endmodule