wave2.v.bak

FPGA的集成开发环境ISE中课仿真的Verilog代码集锦

`timescale 10ns/1ns
module wave2;
reg wave;
parameter cycle=5;

initial fork
              wave=0;
   #(cycle)   wave=1;
   #(2*cycle) wave=0;
   #(3*cycle) wave=1;
   #(4*cycle) wave=0;
   #(5*cycle) wave=1; 
join
initial $monitor($time,"wave=%b",wave);
endmodule]