fpga_seg7_v4.fit.rpt

FPGA应用如sd卡控制

; Auto Packed Registers -- Stratix II/Cyclone II       ; Auto                           ; Auto                           ;
; Auto Delay Chains                                    ; On                             ; On                             ;
; Auto Merge PLLs                                      ; On                             ; On                             ;
; Fitter Effort                                        ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                      ; Normal                         ; Normal                         ;
; Auto Global Clock                                    ; On                             ; On                             ;
; Auto Global Register Control Signals                 ; On                             ; On                             ;
+------------------------------------------------------+--------------------------------+--------------------------------+


+--------------------------------------------------------------------+
; Fitter Device Options                                              ;
+----------------------------------------------+---------------------+
; Option                                       ; Setting             ;
+----------------------------------------------+---------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off                 ;
; Enable device-wide reset (DEV_CLRn)          ; Off                 ;
; Enable device-wide output enable (DEV_OE)    ; Off                 ;
; Enable INIT_DONE output                      ; Off                 ;
; Configuration scheme                         ; Active Serial       ;
; Error detection CRC                          ; Off                 ;
; Reserve ASDO pin after configuration.        ; As input tri-stated ;
; Reserve all unused pins                      ; As input tri-stated ;
; Base pin-out file on sameframe device        ; Off                 ;
+----------------------------------------------+---------------------+


+------------------+
; Fitter Equations ;
+------------------+
The equations can be found in G:/FPGA_SEG7_V4/FPGA_SEG7_V4.fit.eqn.


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in G:/FPGA_SEG7_V4/FPGA_SEG7_V4.pin.


+----------------------------------------------------------------------+
; Fitter Resource Usage Summary                                        ;
+---------------------------------------------+------------------------+
; Resource                                    ; Usage                  ;
+---------------------------------------------+------------------------+
; Total logic elements                        ; 62 / 33,216 ( < 1 % )  ;
;     -- Combinational with no register       ; 19                     ;
;     -- Register only                        ; 0                      ;
;     -- Combinational with a register        ; 43                     ;
;                                             ;                        ;
; Logic element usage by number of LUT inputs ;                        ;
;     -- 4 input functions                    ; 15                     ;
;     -- 3 input functions                    ; 0                      ;
;     -- <=2 input functions                  ; 47                     ;
;     -- Register only                        ; 0                      ;
;         -- Combinational cells for routing  ; 0                      ;
;                                             ;                        ;
; Logic elements by mode                      ;                        ;
;     -- normal mode                          ; 24                     ;
;     -- arithmetic mode                      ; 38                     ;
;                                             ;                        ;
; Total registers                             ; 43 / 33,216 ( < 1 % )  ;
; Total LABs                                  ; 6 / 2,076 ( < 1 % )    ;
; User inserted logic elements                ; 0                      ;
; Virtual pins                                ; 0                      ;
; I/O pins                                    ; 13 / 322 ( 4 % )       ;
;     -- Clock pins                           ; 2 / 8 ( 25 % )         ;
; Global signals                              ; 5                      ;
; M4Ks                                        ; 0 / 105 ( 0 % )        ;
; Total memory bits                           ; 0 / 483,840 ( 0 % )    ;
; Total RAM block bits                        ; 0 / 483,840 ( 0 % )    ;
; Embedded Multiplier 9-bit elements          ; 0 / 70 ( 0 % )         ;
; PLLs                                        ; 0 / 4 ( 0 % )          ;
; Global clocks                               ; 5 / 16 ( 31 % )        ;
; Maximum fan-out node                        ; clk~clkctrl            ;
; Maximum fan-out                             ; 25                     ;
; Highest non-global fan-out signal           ; segmain:inst|comclk[0] ;
; Highest non-global fan-out                  ; 13                     ;
; Total fan-out                               ; 270                    ;
; Average fan-out                             ; 2.16                   ;
+---------------------------------------------+------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins                                                                                                                                                                                                                                                  ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name  ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; clk   ; L1    ; 2        ; 0            ; 18           ; 0           ; 1                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; LVTTL        ; Off         ; User                 ;
; reset ; U12   ; 8        ; 33           ; 0            ; 2           ; 1                     ; 0                  ; no     ; no             ; no            ; no              ; no       ; Off          ; LVTTL        ; Off         ; User                 ;
+-------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins                                                                                                                                                                                                                                                                                 ;
+------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; Name       ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ;
+------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+
; ledcom[0]  ; G20   ; 5        ; 65           ; 31           ; 2           ; no              ; no                     ; no            ; no              ; no         ; no            ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; User                 ; 0 pF ;
; ledcom[1]  ; H14   ; 4        ; 53           ; 36           ; 0           ; no              ; no                     ; no            ; no              ; no         ; no            ; no       ; Off          ; LVTTL        ; 24mA             ; Off         ; User                 ; 0 pF ;