📄 counter32b.rpt
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Device-Specific Information: e:\eda\edakechengsheji\counter32b.rpt
counter32b
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - C 13 AND2 0 2 0 1 |LPM_ADD_SUB:82|addcore:adder|:59
- 8 - C 13 OR2 0 4 0 1 |LPM_ADD_SUB:82|addcore:adder|:77
- 5 - C 13 DFFE + 1 2 1 3 CQI3 (:9)
- 7 - C 13 DFFE + 1 2 1 3 CQI2 (:10)
- 2 - C 13 DFFE + 1 2 1 4 CQI1 (:11)
- 1 - C 13 DFFE + 1 1 1 5 CQI0 (:12)
- 3 - C 13 OR2 0 4 0 4 :48
- 4 - C 13 AND2 0 4 1 0 :194
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\eda\edakechengsheji\counter32b.rpt
counter32b
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 1/ 96( 1%) 0/ 48( 0%) 4/ 48( 8%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\eda\edakechengsheji\counter32b.rpt
counter32b
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 4 CLK
Device-Specific Information: e:\eda\edakechengsheji\counter32b.rpt
counter32b
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 4 CLR
Device-Specific Information: e:\eda\edakechengsheji\counter32b.rpt
counter32b
** EQUATIONS **
CLK : INPUT;
CLR : INPUT;
ENA : INPUT;
-- Node name is 'CARRY_OUT'
-- Equation name is 'CARRY_OUT', type is output
CARRY_OUT = _LC4_C13;
-- Node name is ':12' = 'CQI0'
-- Equation name is 'CQI0', location is LC1_C13, type is buried.
CQI0 = DFFE( _EQ001, GLOBAL( CLK), GLOBAL(!CLR), VCC, VCC);
_EQ001 = !CQI0 & ENA & _LC3_C13
# CQI0 & !ENA;
-- Node name is ':11' = 'CQI1'
-- Equation name is 'CQI1', location is LC2_C13, type is buried.
CQI1 = DFFE( _EQ002, GLOBAL( CLK), GLOBAL(!CLR), VCC, VCC);
_EQ002 = !CQI0 & CQI1 & _LC3_C13
# CQI0 & !CQI1 & ENA & _LC3_C13
# CQI1 & !ENA;
-- Node name is ':10' = 'CQI2'
-- Equation name is 'CQI2', location is LC7_C13, type is buried.
CQI2 = DFFE( _EQ003, GLOBAL( CLK), GLOBAL(!CLR), VCC, VCC);
_EQ003 = CQI2 & _LC3_C13 & !_LC6_C13
# !CQI2 & ENA & _LC3_C13 & _LC6_C13
# CQI2 & !ENA;
-- Node name is ':9' = 'CQI3'
-- Equation name is 'CQI3', location is LC5_C13, type is buried.
CQI3 = DFFE( _EQ004, GLOBAL( CLK), GLOBAL(!CLR), VCC, VCC);
_EQ004 = ENA & _LC3_C13 & _LC8_C13
# CQI3 & !ENA;
-- Node name is 'CQ0'
-- Equation name is 'CQ0', type is output
CQ0 = CQI0;
-- Node name is 'CQ1'
-- Equation name is 'CQ1', type is output
CQ1 = CQI1;
-- Node name is 'CQ2'
-- Equation name is 'CQ2', type is output
CQ2 = CQI2;
-- Node name is 'CQ3'
-- Equation name is 'CQ3', type is output
CQ3 = CQI3;
-- Node name is '|LPM_ADD_SUB:82|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_C13', type is buried
_LC6_C13 = LCELL( _EQ005);
_EQ005 = CQI0 & CQI1;
-- Node name is '|LPM_ADD_SUB:82|addcore:adder|:77' from file "addcore.tdf" line 316, column 45
-- Equation name is '_LC8_C13', type is buried
_LC8_C13 = LCELL( _EQ006);
_EQ006 = !CQI1 & CQI3
# !CQI0 & CQI3
# !CQI2 & CQI3
# CQI0 & CQI1 & CQI2 & !CQI3;
-- Node name is ':48'
-- Equation name is '_LC3_C13', type is buried
_LC3_C13 = LCELL( _EQ007);
_EQ007 = !CQI3
# !CQI0 & !CQI1 & !CQI2;
-- Node name is ':194'
-- Equation name is '_LC4_C13', type is buried
_LC4_C13 = LCELL( _EQ008);
_EQ008 = CQI0 & !CQI1 & !CQI2 & CQI3;
Project Information e:\eda\edakechengsheji\counter32b.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:02
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:03
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,515K
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