📄 reg32b.rpt
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-- Equation name is 'DOUT17', type is output
DOUT17 = _LC1_C7;
-- Node name is 'DOUT18'
-- Equation name is 'DOUT18', type is output
DOUT18 = _LC1_C15;
-- Node name is 'DOUT19'
-- Equation name is 'DOUT19', type is output
DOUT19 = _LC6_B5;
-- Node name is 'DOUT20'
-- Equation name is 'DOUT20', type is output
DOUT20 = _LC2_C10;
-- Node name is 'DOUT21'
-- Equation name is 'DOUT21', type is output
DOUT21 = _LC2_A24;
-- Node name is 'DOUT22'
-- Equation name is 'DOUT22', type is output
DOUT22 = _LC1_C22;
-- Node name is 'DOUT23'
-- Equation name is 'DOUT23', type is output
DOUT23 = _LC1_A17;
-- Node name is 'DOUT24'
-- Equation name is 'DOUT24', type is output
DOUT24 = _LC8_C18;
-- Node name is 'DOUT25'
-- Equation name is 'DOUT25', type is output
DOUT25 = _LC2_C6;
-- Node name is 'DOUT26'
-- Equation name is 'DOUT26', type is output
DOUT26 = _LC2_A21;
-- Node name is 'DOUT27'
-- Equation name is 'DOUT27', type is output
DOUT27 = _LC1_B24;
-- Node name is 'DOUT28'
-- Equation name is 'DOUT28', type is output
DOUT28 = _LC5_A1;
-- Node name is 'DOUT29'
-- Equation name is 'DOUT29', type is output
DOUT29 = _LC7_B19;
-- Node name is 'DOUT30'
-- Equation name is 'DOUT30', type is output
DOUT30 = _LC4_B3;
-- Node name is 'DOUT31'
-- Equation name is 'DOUT31', type is output
DOUT31 = _LC1_A5;
-- Node name is ':34'
-- Equation name is '_LC1_A5', type is buried
_LC1_A5 = DFFE( DIN31, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':36'
-- Equation name is '_LC4_B3', type is buried
_LC4_B3 = DFFE( DIN30, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':38'
-- Equation name is '_LC7_B19', type is buried
_LC7_B19 = DFFE( DIN29, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':40'
-- Equation name is '_LC5_A1', type is buried
_LC5_A1 = DFFE( DIN28, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':42'
-- Equation name is '_LC1_B24', type is buried
_LC1_B24 = DFFE( DIN27, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':44'
-- Equation name is '_LC2_A21', type is buried
_LC2_A21 = DFFE( DIN26, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':46'
-- Equation name is '_LC2_C6', type is buried
_LC2_C6 = DFFE( DIN25, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':48'
-- Equation name is '_LC8_C18', type is buried
_LC8_C18 = DFFE( DIN24, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':50'
-- Equation name is '_LC1_A17', type is buried
_LC1_A17 = DFFE( DIN23, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':52'
-- Equation name is '_LC1_C22', type is buried
_LC1_C22 = DFFE( DIN22, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':54'
-- Equation name is '_LC2_A24', type is buried
_LC2_A24 = DFFE( DIN21, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':56'
-- Equation name is '_LC2_C10', type is buried
_LC2_C10 = DFFE( DIN20, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':58'
-- Equation name is '_LC6_B5', type is buried
_LC6_B5 = DFFE( DIN19, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':60'
-- Equation name is '_LC1_C15', type is buried
_LC1_C15 = DFFE( DIN18, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':62'
-- Equation name is '_LC1_C7', type is buried
_LC1_C7 = DFFE( DIN17, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':64'
-- Equation name is '_LC1_A1', type is buried
_LC1_A1 = DFFE( DIN16, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':66'
-- Equation name is '_LC2_C8', type is buried
_LC2_C8 = DFFE( DIN15, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':68'
-- Equation name is '_LC8_A18', type is buried
_LC8_A18 = DFFE( DIN14, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':70'
-- Equation name is '_LC1_C24', type is buried
_LC1_C24 = DFFE( DIN13, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':72'
-- Equation name is '_LC2_C20', type is buried
_LC2_C20 = DFFE( DIN12, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':74'
-- Equation name is '_LC4_B11', type is buried
_LC4_B11 = DFFE( DIN11, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':76'
-- Equation name is '_LC2_A2', type is buried
_LC2_A2 = DFFE( DIN10, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':78'
-- Equation name is '_LC2_B8', type is buried
_LC2_B8 = DFFE( DIN9, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':80'
-- Equation name is '_LC1_A15', type is buried
_LC1_A15 = DFFE( DIN8, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':82'
-- Equation name is '_LC4_A1', type is buried
_LC4_A1 = DFFE( DIN7, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':84'
-- Equation name is '_LC7_C13', type is buried
_LC7_C13 = DFFE( DIN6, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':86'
-- Equation name is '_LC3_B13', type is buried
_LC3_B13 = DFFE( DIN5, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':88'
-- Equation name is '_LC1_C16', type is buried
_LC1_C16 = DFFE( DIN4, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':90'
-- Equation name is '_LC2_B11', type is buried
_LC2_B11 = DFFE( DIN3, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':92'
-- Equation name is '_LC4_A2', type is buried
_LC4_A2 = DFFE( DIN2, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':94'
-- Equation name is '_LC8_A24', type is buried
_LC8_A24 = DFFE( DIN1, GLOBAL( LOAD), VCC, VCC, VCC);
-- Node name is ':96'
-- Equation name is '_LC1_B1', type is buried
_LC1_B1 = DFFE( DIN0, GLOBAL( LOAD), VCC, VCC, VCC);
Project Information e:\eda\edakechengsheji\reg32b.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'ACEX1K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,863K
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