📄 freqtest.rpt
字号:
A26 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 3/22( 13%)
A28 4/ 8( 50%) 4/ 8( 50%) 0/ 8( 0%) 1/2 0/2 5/22( 22%)
A32 1/ 8( 12%) 1/ 8( 12%) 0/ 8( 0%) 1/2 0/2 2/22( 9%)
A33 6/ 8( 75%) 6/ 8( 75%) 0/ 8( 0%) 1/2 0/2 7/22( 31%)
A35 8/ 8(100%) 8/ 8(100%) 0/ 8( 0%) 1/2 0/2 9/22( 40%)
A36 8/ 8(100%) 6/ 8( 75%) 2/ 8( 25%) 2/2 0/2 8/22( 36%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 2/6 ( 33%)
Total I/O pins used: 32/96 ( 33%)
Total logic cells used: 98/1728 ( 5%)
Total embedded cells used: 0/96 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 2.73/4 ( 68%)
Total fan-in: 268/6912 ( 3%)
Total input pins required: 2
Total input I/O cell registers required: 0
Total output pins required: 32
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 98
Total flipflops required: 65
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 1/1728 ( 0%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 1 0 0 1 0 2 0 2 0 1 0 0 0 0 0 8 8 0 0 8 0 8 8 0 8 8 8 0 4 0 0 0 1 6 0 8 8 98/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
Total: 1 0 0 1 0 2 0 2 0 1 0 0 0 0 0 8 8 0 0 8 0 8 8 0 8 8 8 0 4 0 0 0 1 6 0 8 8 98/0
Device-Specific Information: e:\eda\edakechengsheji\freqtest.rpt
freqtest
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - - -- INPUT G ^ 0 0 0 1 CLK
54 - - - -- INPUT G ^ 0 0 0 0 FSIN
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\eda\edakechengsheji\freqtest.rpt
freqtest
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
30 - - F -- OUTPUT 0 1 0 0 DOUT0
31 - - F -- OUTPUT 0 1 0 0 DOUT1
32 - - F -- OUTPUT 0 1 0 0 DOUT2
33 - - F -- OUTPUT 0 1 0 0 DOUT3
36 - - - 36 OUTPUT 0 1 0 0 DOUT4
37 - - - 35 OUTPUT 0 1 0 0 DOUT5
38 - - - 34 OUTPUT 0 1 0 0 DOUT6
39 - - - 33 OUTPUT 0 1 0 0 DOUT7
41 - - - 31 OUTPUT 0 1 0 0 DOUT8
42 - - - 28 OUTPUT 0 1 0 0 DOUT9
65 - - - 09 OUTPUT 0 1 0 0 DOUT10
67 - - - 08 OUTPUT 0 1 0 0 DOUT11
68 - - - 07 OUTPUT 0 1 0 0 DOUT12
69 - - - 06 OUTPUT 0 1 0 0 DOUT13
70 - - - 05 OUTPUT 0 1 0 0 DOUT14
72 - - - 03 OUTPUT 0 1 0 0 DOUT15
73 - - - 01 OUTPUT 0 1 0 0 DOUT16
78 - - F -- OUTPUT 0 1 0 0 DOUT17
79 - - F -- OUTPUT 0 1 0 0 DOUT18
80 - - F -- OUTPUT 0 1 0 0 DOUT19
81 - - F -- OUTPUT 0 1 0 0 DOUT20
82 - - F -- OUTPUT 0 1 0 0 DOUT21
83 - - E -- OUTPUT 0 1 0 0 DOUT22
86 - - E -- OUTPUT 0 1 0 0 DOUT23
87 - - E -- OUTPUT 0 1 0 0 DOUT24
88 - - D -- OUTPUT 0 1 0 0 DOUT25
89 - - D -- OUTPUT 0 1 0 0 DOUT26
90 - - D -- OUTPUT 0 1 0 0 DOUT27
91 - - D -- OUTPUT 0 1 0 0 DOUT28
92 - - D -- OUTPUT 0 1 0 0 DOUT29
95 - - C -- OUTPUT 0 1 0 0 DOUT30
96 - - C -- OUTPUT 0 1 0 0 DOUT31
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\eda\edakechengsheji\freqtest.rpt
freqtest
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 7 - A 19 AND2 0 2 0 1 |COUNTER32B:2|LPM_ADD_SUB:82|addcore:adder|:59
- 8 - A 19 OR2 0 4 0 1 |COUNTER32B:2|LPM_ADD_SUB:82|addcore:adder|:77
- 2 - A 19 DFFE + 0 4 0 4 |COUNTER32B:2|CQI3 (|COUNTER32B:2|:9)
- 3 - A 19 DFFE + 0 4 0 4 |COUNTER32B:2|CQI2 (|COUNTER32B:2|:10)
- 4 - A 19 DFFE + 0 4 0 5 |COUNTER32B:2|CQI1 (|COUNTER32B:2|:11)
- 5 - A 19 DFFE + 0 3 0 6 |COUNTER32B:2|CQI0 (|COUNTER32B:2|:12)
- 6 - A 19 OR2 0 4 0 4 |COUNTER32B:2|:48
- 1 - A 19 AND2 0 4 0 4 |COUNTER32B:2|:194
- 7 - A 22 AND2 0 2 0 1 |COUNTER32B:3|LPM_ADD_SUB:82|addcore:adder|:59
- 8 - A 22 OR2 0 4 0 1 |COUNTER32B:3|LPM_ADD_SUB:82|addcore:adder|:77
- 3 - A 22 DFFE 0 5 0 4 |COUNTER32B:3|CQI3 (|COUNTER32B:3|:9)
- 2 - A 22 DFFE 0 5 0 4 |COUNTER32B:3|CQI2 (|COUNTER32B:3|:10)
- 4 - A 22 DFFE 0 5 0 5 |COUNTER32B:3|CQI1 (|COUNTER32B:3|:11)
- 5 - A 22 DFFE 0 4 0 6 |COUNTER32B:3|CQI0 (|COUNTER32B:3|:12)
- 6 - A 22 OR2 0 4 0 4 |COUNTER32B:3|:48
- 1 - A 22 AND2 0 4 0 4 |COUNTER32B:3|:194
- 7 - A 17 AND2 0 2 0 1 |COUNTER32B:4|LPM_ADD_SUB:82|addcore:adder|:59
- 8 - A 17 OR2 0 4 0 1 |COUNTER32B:4|LPM_ADD_SUB:82|addcore:adder|:77
- 5 - A 17 DFFE 0 5 0 4 |COUNTER32B:4|CQI3 (|COUNTER32B:4|:9)
- 2 - A 17 DFFE 0 5 0 4 |COUNTER32B:4|CQI2 (|COUNTER32B:4|:10)
- 4 - A 17 DFFE 0 5 0 5 |COUNTER32B:4|CQI1 (|COUNTER32B:4|:11)
- 1 - A 17 DFFE 0 4 0 6 |COUNTER32B:4|CQI0 (|COUNTER32B:4|:12)
- 6 - A 17 OR2 0 4 0 4 |COUNTER32B:4|:48
- 3 - A 17 AND2 0 4 0 4 |COUNTER32B:4|:194
- 7 - A 16 AND2 0 2 0 1 |COUNTER32B:5|LPM_ADD_SUB:82|addcore:adder|:59
- 8 - A 16 OR2 0 4 0 1 |COUNTER32B:5|LPM_ADD_SUB:82|addcore:adder|:77
- 1 - A 16 DFFE 0 5 0 4 |COUNTER32B:5|CQI3 (|COUNTER32B:5|:9)
- 2 - A 16 DFFE 0 5 0 4 |COUNTER32B:5|CQI2 (|COUNTER32B:5|:10)
- 3 - A 16 DFFE 0 5 0 5 |COUNTER32B:5|CQI1 (|COUNTER32B:5|:11)
- 4 - A 16 DFFE 0 4 0 6 |COUNTER32B:5|CQI0 (|COUNTER32B:5|:12)
- 6 - A 16 OR2 0 4 0 4 |COUNTER32B:5|:48
- 5 - A 16 AND2 0 4 0 4 |COUNTER32B:5|:194
- 7 - A 26 AND2 0 2 0 1 |COUNTER32B:6|LPM_ADD_SUB:82|addcore:adder|:59
- 8 - A 26 OR2 0 4 0 1 |COUNTER32B:6|LPM_ADD_SUB:82|addcore:adder|:77
- 1 - A 26 DFFE 0 5 0 4 |COUNTER32B:6|CQI3 (|COUNTER32B:6|:9)
- 5 - A 26 DFFE 0 5 0 4 |COUNTER32B:6|CQI2 (|COUNTER32B:6|:10)
- 3 - A 26 DFFE 0 5 0 5 |COUNTER32B:6|CQI1 (|COUNTER32B:6|:11)
- 4 - A 26 DFFE 0 4 0 6 |COUNTER32B:6|CQI0 (|COUNTER32B:6|:12)
- 6 - A 26 OR2 0 4 0 4 |COUNTER32B:6|:48
- 2 - A 26 AND2 0 4 0 4 |COUNTER32B:6|:194
- 7 - A 21 AND2 0 2 0 1 |COUNTER32B:7|LPM_ADD_SUB:82|addcore:adder|:59
- 8 - A 21 OR2 0 4 0 1 |COUNTER32B:7|LPM_ADD_SUB:82|addcore:adder|:77
- 4 - A 21 DFFE 0 5 0 4 |COUNTER32B:7|CQI3 (|COUNTER32B:7|:9)
- 5 - A 21 DFFE 0 5 0 4 |COUNTER32B:7|CQI2 (|COUNTER32B:7|:10)
- 2 - A 21 DFFE 0 5 0 5 |COUNTER32B:7|CQI1 (|COUNTER32B:7|:11)
- 1 - A 21 DFFE 0 4 0 6 |COUNTER32B:7|CQI0 (|COUNTER32B:7|:12)
- 6 - A 21 OR2 0 4 0 4 |COUNTER32B:7|:48
- 3 - A 21 AND2 0 4 0 4 |COUNTER32B:7|:194
- 7 - A 24 AND2 0 2 0 1 |COUNTER32B:8|LPM_ADD_SUB:82|addcore:adder|:59
- 8 - A 24 OR2 0 4 0 1 |COUNTER32B:8|LPM_ADD_SUB:82|addcore:adder|:77
- 3 - A 24 DFFE 0 5 0 4 |COUNTER32B:8|CQI3 (|COUNTER32B:8|:9)
- 2 - A 24 DFFE 0 5 0 4 |COUNTER32B:8|CQI2 (|COUNTER32B:8|:10)
- 1 - A 24 DFFE 0 5 0 5 |COUNTER32B:8|CQI1 (|COUNTER32B:8|:11)
- 5 - A 24 DFFE 0 4 0 6 |COUNTER32B:8|CQI0 (|COUNTER32B:8|:12)
- 6 - A 24 OR2 0 4 0 4 |COUNTER32B:8|:48
- 4 - A 24 AND2 0 4 0 4 |COUNTER32B:8|:194
- 7 - A 25 AND2 0 2 0 1 |COUNTER32B:9|LPM_ADD_SUB:82|addcore:adder|:59
- 8 - A 25 OR2 0 4 0 1 |COUNTER32B:9|LPM_ADD_SUB:82|addcore:adder|:77
- 5 - A 25 DFFE 0 5 0 4 |COUNTER32B:9|CQI3 (|COUNTER32B:9|:9)
- 4 - A 25 DFFE 0 5 0 4 |COUNTER32B:9|CQI2 (|COUNTER32B:9|:10)
- 3 - A 25 DFFE 0 5 0 5 |COUNTER32B:9|CQI1 (|COUNTER32B:9|:11)
- 2 - A 25 DFFE 0 4 0 6 |COUNTER32B:9|CQI0 (|COUNTER32B:9|:12)
- 6 - A 25 OR2 0 4 0 4 |COUNTER32B:9|:48
- 1 - A 25 OR2 s 0 3 0 1 |COUNTER32B:9|~194~1
- 3 - A 36 DFFE + 0 0 0 65 |FTCTRL:10|Div2CLK (|FTCTRL:10|:5)
- 2 - A 36 OR2 ! 1 3 0 32 |HUO:18|:13
- 4 - A 36 DFFE 0 2 1 0 |REG32B:11|:34
- 8 - A 35 DFFE 0 2 1 0 |REG32B:11|:36
- 1 - A 33 DFFE 0 2 1 0 |REG32B:11|:38
- 3 - A 35 DFFE 0 2 1 0 |REG32B:11|:40
- 5 - A 35 DFFE 0 2 1 0 |REG32B:11|:42
- 6 - A 33 DFFE 0 2 1 0 |REG32B:11|:44
- 8 - A 36 DFFE 0 2 1 0 |REG32B:11|:46
- 1 - A 36 DFFE 0 2 1 0 |REG32B:11|:48
- 4 - A 33 DFFE 0 2 1 0 |REG32B:11|:50
- 8 - A 28 DFFE 0 2 1 0 |REG32B:11|:52
- 1 - A 28 DFFE 0 2 1 0 |REG32B:11|:54
- 2 - A 35 DFFE 0 2 1 0 |REG32B:11|:56
- 4 - A 35 DFFE 0 2 1 0 |REG32B:11|:58
- 6 - A 35 DFFE 0 2 1 0 |REG32B:11|:60
- 8 - A 33 DFFE 0 2 1 0 |REG32B:11|:62
- 1 - A 01 DFFE 0 2 1 0 |REG32B:11|:64
- 4 - A 04 DFFE 0 2 1 0 |REG32B:11|:66
- 4 - A 06 DFFE 0 2 1 0 |REG32B:11|:68
- 1 - A 06 DFFE 0 2 1 0 |REG32B:11|:70
- 4 - A 08 DFFE 0 2 1 0 |REG32B:11|:72
- 1 - A 08 DFFE 0 2 1 0 |REG32B:11|:74
- 4 - A 10 DFFE 0 2 1 0 |REG32B:11|:76
- 3 - A 28 DFFE 0 2 1 0 |REG32B:11|:78
- 4 - A 32 DFFE 0 2 1 0 |REG32B:11|:80
- 7 - A 33 DFFE 0 2 1 0 |REG32B:11|:82
- 2 - A 33 DFFE 0 2 1 0 |REG32B:11|:84
- 7 - A 35 DFFE 0 2 1 0 |REG32B:11|:86
- 6 - A 36 DFFE 0 2 1 0 |REG32B:11|:88
- 7 - A 36 DFFE 0 2 1 0 |REG32B:11|:90
- 5 - A 36 DFFE 0 2 1 0 |REG32B:11|:92
- 2 - A 28 DFFE 0 2 1 0 |REG32B:11|:94
- 1 - A 35 DFFE 0 2 1 0 |REG32B:11|:96
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\eda\edakechengsheji\freqtest.rpt
freqtest
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 7/144( 4%) 7/ 72( 9%) 28/ 72( 38%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 0/144( 0%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 2/144( 1%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
D: 5/144( 3%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
E: 3/144( 2%) 0/ 72( 0%) 0/ 72( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
F: 5/144( 3%) 0/ 72( 0%) 4/ 72( 5%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
Column FastTrack Interconnect:
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