rece11.vhd

分别完成了异步发送电路

-- expected framing_error
t_prcs_framing_error: PROCESS
BEGIN
	t_sig_o4_expected <= '0';
WAIT;
END PROCESS t_prcs_framing_error;

-- expected IQR
t_prcs_IQR: PROCESS
BEGIN
	t_sig_o5_expected <= '0';
WAIT;
END PROCESS t_prcs_IQR;

-- expected overrun_error
t_prcs_overrun_error: PROCESS
BEGIN
	t_sig_o6_expected <= '0';
WAIT;
END PROCESS t_prcs_overrun_error;

-- expected parity_error
t_prcs_parity_error: PROCESS
BEGIN
	t_sig_o7_expected <= '0';
WAIT;
END PROCESS t_prcs_parity_error;

-- Set trigger on real/expected o/ pattern changes                        

t_prcs_trigger_e : PROCESS(t_sig_o1_expected,t_sig_o2_expected,t_sig_o3_expected,t_sig_o4_expected,t_sig_o5_expected,t_sig_o6_expected,t_sig_o7_expected)
BEGIN
	trigger_e <= NOT trigger_e;
END PROCESS t_prcs_trigger_e;

t_prcs_trigger_r : PROCESS(o1,o2,o3,o4,o5,o6,o7)
BEGIN
	trigger_r <= NOT trigger_r;
END PROCESS t_prcs_trigger_r;


t_prcs_selfcheck : PROCESS
VARIABLE i : INTEGER := 1;
VARIABLE txt : LINE;

VARIABLE last_o1_exp : o1_type := 'U';
VARIABLE last_o2_exp : o2_type := 'U';
VARIABLE last_o3_exp : o3_type := (OTHERS => 'U');
VARIABLE last_o4_exp : o4_type := 'U';
VARIABLE last_o5_exp : o5_type := 'U';
VARIABLE last_o6_exp : o6_type := 'U';
VARIABLE last_o7_exp : o7_type := 'U';

VARIABLE on_first_change : trackvec := "1111111";
BEGIN

WAIT UNTIL (sampler'LAST_VALUE = '1'OR sampler'LAST_VALUE = '0')
	AND sampler'EVENT;
IF (debug_tbench = '1') THEN
	write(txt,string'("Scanning pattern "));
	write(txt,i);
	writeline(output,txt);
	write(txt,string'("| expected "));write(txt,o1_name);write(txt,string'(" = "));write(txt,t_sig_o1_expected_prev);
	write(txt,string'("| expected "));write(txt,o2_name);write(txt,string'(" = "));write(txt,t_sig_o2_expected_prev);
	write(txt,string'("| expected "));write(txt,o3_name);write(txt,string'(" = "));write(txt,t_sig_o3_expected_prev);
	write(txt,string'("| expected "));write(txt,o4_name);write(txt,string'(" = "));write(txt,t_sig_o4_expected_prev);
	write(txt,string'("| expected "));write(txt,o5_name);write(txt,string'(" = "));write(txt,t_sig_o5_expected_prev);
	write(txt,string'("| expected "));write(txt,o6_name);write(txt,string'(" = "));write(txt,t_sig_o6_expected_prev);
	write(txt,string'("| expected "));write(txt,o7_name);write(txt,string'(" = "));write(txt,t_sig_o7_expected_prev);
	writeline(output,txt);
	write(txt,string'("| real "));write(txt,o1_name);write(txt,string'(" = "));write(txt,t_sig_o1_prev);
	write(txt,string'("| real "));write(txt,o2_name);write(txt,string'(" = "));write(txt,t_sig_o2_prev);
	write(txt,string'("| real "));write(txt,o3_name);write(txt,string'(" = "));write(txt,t_sig_o3_prev);
	write(txt,string'("| real "));write(txt,o4_name);write(txt,string'(" = "));write(txt,t_sig_o4_prev);
	write(txt,string'("| real "));write(txt,o5_name);write(txt,string'(" = "));write(txt,t_sig_o5_prev);
	write(txt,string'("| real "));write(txt,o6_name);write(txt,string'(" = "));write(txt,t_sig_o6_prev);
	write(txt,string'("| real "));write(txt,o7_name);write(txt,string'(" = "));write(txt,t_sig_o7_prev);
	writeline(output,txt);
	i := i + 1;
END IF;
IF ( t_sig_o1_expected_prev /= 'X' ) AND (t_sig_o1_expected_prev /= 'U' ) AND (t_sig_o1_prev /= t_sig_o1_expected_prev) AND (
	(t_sig_o1_expected_prev /= last_o1_exp) OR
	(on_first_change(1) = '1')
		) THEN
	throw_error("clk46",t_sig_o1_expected_prev,t_sig_o1_prev);
	num_mismatches(0) <= num_mismatches(0) + 1;
	on_first_change(1) := '0';
	last_o1_exp := t_sig_o1_expected_prev;
END IF;
IF ( t_sig_o2_expected_prev /= 'X' ) AND (t_sig_o2_expected_prev /= 'U' ) AND (t_sig_o2_prev /= t_sig_o2_expected_prev) AND (
	(t_sig_o2_expected_prev /= last_o2_exp) OR
	(on_first_change(2) = '1')
		) THEN
	throw_error("data_ready",t_sig_o2_expected_prev,t_sig_o2_prev);
	num_mismatches(1) <= num_mismatches(1) + 1;
	on_first_change(2) := '0';
	last_o2_exp := t_sig_o2_expected_prev;
END IF;
IF ( t_sig_o3_expected_prev /= "XXXXXXXX" ) AND (t_sig_o3_expected_prev /= "UUUUUUUU" ) AND (t_sig_o3_prev /= t_sig_o3_expected_prev) AND (
	(t_sig_o3_expected_prev /= last_o3_exp) OR
	(on_first_change(3) = '1')
		) THEN
	throw_error("dout",t_sig_o3_expected_prev,t_sig_o3_prev);
	num_mismatches(2) <= num_mismatches(2) + 1;
	on_first_change(3) := '0';
	last_o3_exp := t_sig_o3_expected_prev;
END IF;
IF ( t_sig_o4_expected_prev /= 'X' ) AND (t_sig_o4_expected_prev /= 'U' ) AND (t_sig_o4_prev /= t_sig_o4_expected_prev) AND (
	(t_sig_o4_expected_prev /= last_o4_exp) OR
	(on_first_change(4) = '1')
		) THEN
	throw_error("framing_error",t_sig_o4_expected_prev,t_sig_o4_prev);
	num_mismatches(3) <= num_mismatches(3) + 1;
	on_first_change(4) := '0';
	last_o4_exp := t_sig_o4_expected_prev;
END IF;
IF ( t_sig_o5_expected_prev /= 'X' ) AND (t_sig_o5_expected_prev /= 'U' ) AND (t_sig_o5_prev /= t_sig_o5_expected_prev) AND (
	(t_sig_o5_expected_prev /= last_o5_exp) OR
	(on_first_change(5) = '1')
		) THEN
	throw_error("IQR",t_sig_o5_expected_prev,t_sig_o5_prev);
	num_mismatches(4) <= num_mismatches(4) + 1;
	on_first_change(5) := '0';
	last_o5_exp := t_sig_o5_expected_prev;
END IF;
IF ( t_sig_o6_expected_prev /= 'X' ) AND (t_sig_o6_expected_prev /= 'U' ) AND (t_sig_o6_prev /= t_sig_o6_expected_prev) AND (
	(t_sig_o6_expected_prev /= last_o6_exp) OR
	(on_first_change(6) = '1')
		) THEN
	throw_error("overrun_error",t_sig_o6_expected_prev,t_sig_o6_prev);
	num_mismatches(5) <= num_mismatches(5) + 1;
	on_first_change(6) := '0';
	last_o6_exp := t_sig_o6_expected_prev;
END IF;
IF ( t_sig_o7_expected_prev /= 'X' ) AND (t_sig_o7_expected_prev /= 'U' ) AND (t_sig_o7_prev /= t_sig_o7_expected_prev) AND (
	(t_sig_o7_expected_prev /= last_o7_exp) OR
	(on_first_change(7) = '1')
		) THEN
	throw_error("parity_error",t_sig_o7_expected_prev,t_sig_o7_prev);
	num_mismatches(6) <= num_mismatches(6) + 1;
	on_first_change(7) := '0';
	last_o7_exp := t_sig_o7_expected_prev;
END IF;
    trigger_i <= NOT trigger_i;
END PROCESS t_prcs_selfcheck;


t_prcs_trigger_res : PROCESS(trigger_e,trigger_i,trigger_r)
BEGIN
	trigger <= trigger_i XOR trigger_e XOR trigger_r;
END PROCESS t_prcs_trigger_res;

t_prcs_endsim : PROCESS
VARIABLE txt : LINE;
VARIABLE total_mismatches : INTEGER := 0;
BEGIN
WAIT FOR 300000000 ps;
total_mismatches := num_mismatches(0) + num_mismatches(1) + num_mismatches(2) + num_mismatches(3) + num_mismatches(4) + num_mismatches(5) + num_mismatches(6);
IF (total_mismatches = 0) THEN                                              
        write(txt,string'("Simulation passed !"));                        
        writeline(output,txt);                                              
ELSE                                                                        
        write(txt,total_mismatches);                                        
        write(txt,string'(" mismatched vectors : Simulation failed !"));  
        writeline(output,txt);                                              
END IF;                                                                     
WAIT;
END PROCESS t_prcs_endsim;

END ovec_arch;

LIBRARY ieee;                                               
USE ieee.std_logic_1164.all;                                

LIBRARY STD;                                                            
USE STD.textio.ALL;                                                     

USE WORK.receiver_vhd_tb_types.ALL;                                         

ENTITY receiver_vhd_vec_tst IS
END receiver_vhd_vec_tst;
ARCHITECTURE receiver_arch OF receiver_vhd_vec_tst IS
-- constants                                                 
-- signals                                                   
SIGNAL t_sig_clk : STD_LOGIC;
SIGNAL t_sig_clk46 : STD_LOGIC;
SIGNAL t_sig_data_ready : STD_LOGIC;
SIGNAL t_sig_dout : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL t_sig_ERBF : STD_LOGIC;
SIGNAL t_sig_framing_error : STD_LOGIC;
SIGNAL t_sig_IQR : STD_LOGIC;
SIGNAL t_sig_overrun_error : STD_LOGIC;
SIGNAL t_sig_parity_error : STD_LOGIC;
SIGNAL t_sig_rst : STD_LOGIC;
SIGNAL t_sig_rxd : STD_LOGIC;
SIGNAL t_sig_sampler : sample_type;

COMPONENT receiver
	PORT (
	clk : IN STD_LOGIC;
	clk46 : OUT STD_LOGIC;
	data_ready : OUT STD_LOGIC;
	dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
	ERBF : IN STD_LOGIC;
	framing_error : OUT STD_LOGIC;
	IQR : OUT STD_LOGIC;
	overrun_error : OUT STD_LOGIC;
	parity_error : OUT STD_LOGIC;
	rst : IN STD_LOGIC;
	rxd : IN STD_LOGIC
	);
END COMPONENT;
COMPONENT receiver_vhd_check_tst
PORT (
	o1 : IN o1_type;
	o2 : IN o2_type;
	o3 : IN o3_type;
	o4 : IN o4_type;
	o5 : IN o5_type;
	o6 : IN o6_type;
	o7 : IN o7_type;
	sampler : IN sample_type
);
END COMPONENT;
COMPONENT receiver_vhd_sample_tst
PORT (
	s1 : IN i1_type;
	s2 : IN i2_type;
	s3 : IN i3_type;
	s4 : IN i4_type;
	sampler : OUT sample_type
	);
END COMPONENT;
BEGIN
	i1 : receiver
	PORT MAP (
-- list connections between master ports and signals
	clk => t_sig_clk,
	clk46 => t_sig_clk46,
	data_ready => t_sig_data_ready,
	dout => t_sig_dout,
	ERBF => t_sig_ERBF,
	framing_error => t_sig_framing_error,
	IQR => t_sig_IQR,
	overrun_error => t_sig_overrun_error,
	parity_error => t_sig_parity_error,
	rst => t_sig_rst,
	rxd => t_sig_rxd
	);

-- clk
t_prcs_clk: PROCESS
BEGIN
LOOP
	t_sig_clk <= '0';
	WAIT FOR 200000 ps;
	t_sig_clk <= '1';
	WAIT FOR 200000 ps;
	IF (NOW >= 300000000 ps) THEN WAIT; END IF;
END LOOP;
END PROCESS t_prcs_clk;

-- rst
t_prcs_rst: PROCESS
BEGIN
	t_sig_rst <= '0';
	WAIT FOR 800000 ps;
	t_sig_rst <= '1';
	WAIT FOR 800000 ps;
	t_sig_rst <= '0';
WAIT;
END PROCESS t_prcs_rst;

-- rxd
t_prcs_rxd: PROCESS
BEGIN
	t_sig_rxd <= '1';
	WAIT FOR 8800000 ps;
	t_sig_rxd <= '0';
	WAIT FOR 18800000 ps;
	t_sig_rxd <= '1';
	WAIT FOR 18400000 ps;
	t_sig_rxd <= '0';
	WAIT FOR 18400000 ps;
	t_sig_rxd <= '1';
	WAIT FOR 18400000 ps;
	t_sig_rxd <= '0';
	WAIT FOR 18400000 ps;
	t_sig_rxd <= '1';
	WAIT FOR 18400000 ps;
	t_sig_rxd <= '0';
	WAIT FOR 18400000 ps;
	t_sig_rxd <= '1';
	WAIT FOR 18800000 ps;
	t_sig_rxd <= '0';
	WAIT FOR 18000000 ps;
	t_sig_rxd <= '1';
WAIT;
END PROCESS t_prcs_rxd;

-- ERBF
t_prcs_ERBF: PROCESS
BEGIN
	t_sig_ERBF <= '0';
WAIT;
END PROCESS t_prcs_ERBF;
tb_sample : receiver_vhd_sample_tst
PORT MAP (
	s1 => t_sig_clk,
	s2 => t_sig_ERBF,
	s3 => t_sig_rst,
	s4 => t_sig_rxd,
	sampler => t_sig_sampler
	);

tb_out : receiver_vhd_check_tst
PORT MAP (
	o1 => t_sig_clk46,
	o2 => t_sig_data_ready,
	o3 => t_sig_dout,
	o4 => t_sig_framing_error,
	o5 => t_sig_IQR,
	o6 => t_sig_overrun_error,
	o7 => t_sig_parity_error,
	sampler => t_sig_sampler
	);
END receiver_arch;