📄 trans21.vhd
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-- Copyright (C) 1991-2006 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- *****************************************************************************
-- This file contains a Vhdl test bench with test vectors .The test vectors
-- are exported from a vector file in the Quartus Waveform Editor and apply to
-- the top level entity of the current Quartus project .The user can use this
-- testbench to simulate his design using a third-party simulation tool .
-- *****************************************************************************
-- Generated on "09/12/2008 08:43:17"
-- Vhdl Self-Checking Test Bench (with test vectors) for design : trans_port
--
-- Simulation tool : 3rd Party
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY STD;
USE STD.textio.ALL;
PACKAGE trans_port_vhd_tb_types IS
-- input port types
SUBTYPE i1_type IS STD_LOGIC;
SUBTYPE i2_type IS STD_LOGIC_VECTOR(7 DOWNTO 0);
SUBTYPE i3_type IS STD_LOGIC;
SUBTYPE i4_type IS STD_LOGIC;
SUBTYPE i5_type IS STD_LOGIC;
-- output port types
SUBTYPE o1_type IS STD_LOGIC;
SUBTYPE o2_type IS STD_LOGIC;
-- output port names
CONSTANT o1_name : STRING (1 TO 3) := "IRQ";
CONSTANT o2_name : STRING (1 TO 4) := "sout";
-- n(outputs)
CONSTANT o_num : INTEGER := 2;
-- mismatches vector type
TYPE mmvec IS ARRAY (0 to (o_num - 1)) OF INTEGER;
-- exp o/ first change track vector type
TYPE trackvec IS ARRAY (1 to o_num) OF BIT;
-- sampler type
SUBTYPE sample_type IS STD_LOGIC;
-- utility functions
FUNCTION std_logic_to_char (a: STD_LOGIC) RETURN CHARACTER;
FUNCTION std_logic_vector_to_string (a: STD_LOGIC_VECTOR) RETURN STRING;
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC; justified: IN SIDE:= RIGHT; field:IN WIDTH:=0);
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC_VECTOR; justified: IN SIDE:= RIGHT; field:IN WIDTH:=0);
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC; real_value : IN STD_LOGIC);
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC_VECTOR; real_value : IN STD_LOGIC_VECTOR);
END trans_port_vhd_tb_types;
PACKAGE BODY trans_port_vhd_tb_types IS
FUNCTION std_logic_to_char (a: STD_LOGIC)
RETURN CHARACTER IS
BEGIN
CASE a IS
WHEN 'U' =>
RETURN 'U';
WHEN 'X' =>
RETURN 'X';
WHEN '0' =>
RETURN '0';
WHEN '1' =>
RETURN '1';
WHEN 'Z' =>
RETURN 'Z';
WHEN 'W' =>
RETURN 'W';
WHEN 'L' =>
RETURN 'L';
WHEN 'H' =>
RETURN 'H';
WHEN '-' =>
RETURN 'D';
END CASE;
END;
FUNCTION std_logic_vector_to_string (a: STD_LOGIC_VECTOR)
RETURN STRING IS
VARIABLE result : STRING(1 TO a'LENGTH);
VARIABLE j : NATURAL := 1;
BEGIN
FOR i IN a'RANGE LOOP
result(j) := std_logic_to_char(a(i));
j := j + 1;
END LOOP;
RETURN result;
END;
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC; justified: IN SIDE:=RIGHT; field:IN WIDTH:=0) IS
BEGIN
write(L,std_logic_to_char(VALUE),JUSTIFIED,field);
END;
PROCEDURE write (l:INOUT LINE; value:IN STD_LOGIC_VECTOR; justified: IN SIDE:= RIGHT; field:IN WIDTH:=0) IS
BEGIN
write(L,std_logic_vector_to_string(VALUE),JUSTIFIED,field);
END;
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC; real_value : IN STD_LOGIC) IS
VARIABLE txt : LINE;
BEGIN
write(txt,string'("ERROR! Vector Mismatch for output port "));
write(txt,output_port_name);
write(txt,string'(" :: @time = "));
write(txt,NOW);
write(txt,string'(", Expected value = "));
write(txt,expected_value);
write(txt,string'(", Real value = "));
write(txt,real_value);
writeline(output,txt);
END;
PROCEDURE throw_error(output_port_name: IN STRING; expected_value : IN STD_LOGIC_VECTOR; real_value : IN STD_LOGIC_VECTOR) IS
VARIABLE txt : LINE;
BEGIN
write(txt,string'("ERROR! Vector Mismatch for output port "));
write(txt,output_port_name);
write(txt,string'(" :: @time = "));
write(txt,NOW);
write(txt,string'(", Expected value = "));
write(txt,expected_value);
write(txt,string'(", Real value = "));
write(txt,real_value);
writeline(output,txt);
END;
END trans_port_vhd_tb_types;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE WORK.trans_port_vhd_tb_types.ALL;
ENTITY trans_port_vhd_sample_tst IS
PORT (
s1 : IN i1_type;
s2 : IN i2_type;
s3 : IN i3_type;
s4 : IN i4_type;
s5 : IN i5_type;
sampler : OUT sample_type
);
END trans_port_vhd_sample_tst;
ARCHITECTURE sample_arch OF trans_port_vhd_sample_tst IS
SIGNAL clk : sample_type := '1';
BEGIN
t_prcs_sample : PROCESS ( s1 , s2 , s3 , s4 , s5 )
BEGIN
IF (NOW > 0 ps) AND (NOW < 300000000 ps) THEN
clk <= NOT clk ;
END IF;
END PROCESS t_prcs_sample;
sampler <= clk;
END sample_arch;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY STD;
USE STD.textio.ALL;
USE WORK.trans_port_vhd_tb_types.ALL;
ENTITY trans_port_vhd_check_tst IS
GENERIC (
debug_tbench : BIT := '0'
);
PORT (
o1 : IN o1_type;
o2 : IN o2_type;
sampler : IN sample_type
);
END trans_port_vhd_check_tst;
ARCHITECTURE ovec_arch OF trans_port_vhd_check_tst IS
SIGNAL t_sig_o1_expected,t_sig_o1_expected_prev,t_sig_o1_prev : o1_type;
SIGNAL t_sig_o2_expected,t_sig_o2_expected_prev,t_sig_o2_prev : o2_type;
SIGNAL trigger : BIT := '0';
SIGNAL trigger_e : BIT := '0';
SIGNAL trigger_r : BIT := '0';
SIGNAL trigger_i : BIT := '0';
SIGNAL num_mismatches : mmvec := (OTHERS => 0);
BEGIN
-- Update history buffers expected /o
t_prcs_update_o_expected_hist : PROCESS (trigger)
BEGIN
t_sig_o1_expected_prev <= t_sig_o1_expected;
t_sig_o2_expected_prev <= t_sig_o2_expected;
END PROCESS t_prcs_update_o_expected_hist;
-- Update history buffers real /o
t_prcs_update_o_real_hist : PROCESS (trigger)
BEGIN
t_sig_o1_prev <= o1;
t_sig_o2_prev <= o2;
END PROCESS t_prcs_update_o_real_hist;
-- expected IRQ
t_prcs_IRQ: PROCESS
BEGIN
t_sig_o1_expected <= '0';
WAIT FOR 121808000 ps;
t_sig_o1_expected <= '1';
WAIT FOR 9600000 ps;
t_sig_o1_expected <= '0';
WAIT;
END PROCESS t_prcs_IRQ;
-- expected sout
t_prcs_sout: PROCESS
BEGIN
t_sig_o2_expected <= '0';
WAIT FOR 208000 ps;
t_sig_o2_expected <= '1';
WAIT FOR 610000 ps;
t_sig_o2_expected <= '0';
WAIT FOR 990000 ps;
t_sig_o2_expected <= '1';
WAIT FOR 20000000 ps;
t_sig_o2_expected <= '0';
WAIT FOR 37600000 ps;
t_sig_o2_expected <= '1';
WAIT FOR 18800000 ps;
t_sig_o2_expected <= '0';
WAIT FOR 37600000 ps;
t_sig_o2_expected <= '1';
WAIT FOR 28400000 ps;
t_sig_o2_expected <= '0';
WAIT FOR 37600000 ps;
t_sig_o2_expected <= '1';
WAIT FOR 18800000 ps;
t_sig_o2_expected <= '0';
WAIT FOR 18800000 ps;
t_sig_o2_expected <= '1';
WAIT;
END PROCESS t_prcs_sout;
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