accumulater.vhd

来自「分别用分频比交错法及累加器分频法完成非整数分频器设计。」· VHDL 代码 · 共 34 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity accumulater  is
port(F_IN: in std_logic;
	  reset:in std_logic;
	  F_OUT2: out std_logic);
end;

architecture b of accumulater is
constant step :integer :=131988199;
signal counter :std_logic_vector(29 downto 0):="000000000000000000000000000000";
signal out2:std_logic;


begin
process(F_IN,reset)
begin
if (reset='1') then 
counter<="000000000000000000000000000000";
elsif(F_IN'event and F_IN='1')then
   

       counter<=counter+step;
end if;


end process;

F_OUT2<=counter(29);

 

end;