ctrol.vhd

分别用分频比交错法及累加器分频法完成非整数分频器设计。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ctrol is
port(F_IN:in std_logic;  
		C_ENB:in std_logic;
		FS_CTL:out std_logic);
end ctrol;
architecture behave of ctrol is
signal cnt:integer range 0 to 36;
begin
process(F_IN)
begin
if(F_IN'event and F_IN='0')then
   if(C_ENB='1')then
      if(cnt=36)then cnt<=0;
      else cnt<=cnt+1;end if;
   else cnt<=cnt;end if;
end if;
end process;
      
process(F_IN)
begin
if(F_IN'event and F_IN='1')then
case(cnt)is
       when 0=>FS_CTL<='0';
       when 1=>FS_CTL<='1';
       when 2=>FS_CTL<='1';
       when 3=>FS_CTL<='1';
       when 4=>FS_CTL<='1';
       when 5=>FS_CTL<='1';
       when 6=>FS_CTL<='1';
       when 7=>FS_CTL<='0';
       when 8=>FS_CTL<='1';
       when 9=>FS_CTL<='1';
       when 10=>FS_CTL<='1';
       when 11=>FS_CTL<='1';
       when 12=>FS_CTL<='1';
       when 13=>FS_CTL<='1';
       when 14=>FS_CTL<='1';
       when 15=>FS_CTL<='0';
       when 16=>FS_CTL<='1';
       when 17=>FS_CTL<='1';
       when 18=>FS_CTL<='1';
       when 19=>FS_CTL<='1';
       when 20=>FS_CTL<='1';
       when 21=>FS_CTL<='1';
       when 22=>FS_CTL<='0';
       when 23=>FS_CTL<='1';
       when 24=>FS_CTL<='1';
       when 25=>FS_CTL<='1';
       when 26=>FS_CTL<='1';
       when 27=>FS_CTL<='1';
       when 28=>FS_CTL<='1';
       when 29=>FS_CTL<='1';
       when 30=>FS_CTL<='0';
       when 31=>FS_CTL<='1';
       when 32=>FS_CTL<='1';
       when 33=>FS_CTL<='1';
       when 34=>FS_CTL<='1';
       when 35=>FS_CTL<='1';
       when others=>FS_CTL<='1';
    end case;
end if;
end process;
end;