div89.vhd

分别用分频比交错法及累加器分频法完成非整数分频器设计。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity div89 is
port(F_IN:in std_logic;
         reset:in std_logic;
         F_out1:out std_logic);
end div89;
		
architecture a of div89 is
component div9
    port(clk1:in std_logic;      
         reset:in std_logic;
         C_ENB1:out std_logic;
         cout1:out std_logic);
  end component;
			
component div8
    port(clk2:in std_logic;
         reset:in std_logic;
         C_ENB2:out std_logic;
         cout2:out std_logic);
  end component;

component ctrol
    port(F_IN:in std_logic;  
		C_ENB:in std_logic;
		FS_CTL:out std_logic);
end component;			

signal C_ENB,C_ENB1,C_ENB2: std_logic;
signal FS_CTL: std_logic;
signal clk1,clk2:std_logic;
signal cout1,cout2:std_logic;

begin
process(FS_CTL,F_IN)
begin
if(FS_CTL='0')then 
clk1<=F_IN; clk2<='0';
elsif(FS_CTL='1')then
clk1<='0';clk2<=not F_IN;
end if;
end process;


process(F_IN)
begin
if(F_IN'event and F_IN='1')then
case(FS_CTL)is
   when '0' =>F_OUT1<=cout1;C_ENB<=C_ENB1;
   when others=>F_OUT1<=cout2;C_ENB<=C_ENB2;
end case;
end if;
end process;
  
 
f1:div9 port map(clk1,reset,C_ENB1,cout1);
f2:div8 port map(clk2,reset,C_ENB2,cout2);
f3:ctrol port map(F_IN,C_ENB,FS_CTL);
end;