fy12.v

来自「基于ATEREAL EPM1270T144C5N CPLD 压力传感器数据采集原」· Verilog 代码 · 共 30 行

module fy12(xt1,xt2,xt3,xt4,d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,clk_filter);
input  xt1,xt2,xt3,xt4;
input  d1,d2,d3,d4;
input  d5,d6,d7,d8;
input  d9,d10,d11,d12;
output clk_filter;
reg    clk_filter;
reg[3:0] tep;
    
always @(xt1 or xt2 or xt3 or xt4)
begin
tep<={xt1,xt2,xt3,xt4};
case(tep)
    4'b0000: clk_filter<=d1;
	4'b0001: clk_filter<=d2;
	4'b0010: clk_filter<=d3;
	4'b0011: clk_filter<=d4;
    4'b0100: clk_filter<=d5;
	4'b0101: clk_filter<=d6;
	4'b0110: clk_filter<=d7;
	4'b0111: clk_filter<=d8;
    4'b1000: clk_filter<=d9;
	4'b1001: clk_filter<=d10;
	4'b1010: clk_filter<=d11;
	4'b1011: clk_filter<=d12;
	default: clk_filter<=d12;
endcase
end

endmodule