prev_cmp_ps2.qmsg

使用FPGA读取键盘的例子

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Create VHDL File Quartus II " "Info: Running Quartus II Create VHDL File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Web Edition " "Info: Version 9.0 Build 132 02/25/2009 SJ Web Edition" {  } {  } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Sun Apr 19 10:36:52 2009 " "Info: Processing started: Sun Apr 19 10:36:52 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off PS2 -c PS2 --convert_bdf_to_vhdl=H:/New_file/EP1C12_Examples/PS2_1c12/PS2.bdf " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off PS2 -c PS2 --convert_bdf_to_vhdl=H:/New_file/EP1C12_Examples/PS2_1c12/PS2.bdf" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "PS2.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file PS2.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 PS2 " "Info: Found entity 1: PS2" {  } { { "H:/New_file/EP1C12_Examples/PS2_1c12/PS2.bdf" "" { Schematic "H:/New_file/EP1C12_Examples/PS2_1c12/PS2.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" " " "Info: Elaborating entity \"\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Warning" "WGDFX_INCONSISTENT_DIMENSION" "data " "Warning: Found inconsistent dimensions for element \"data\"" {  } { { "H:/New_file/EP1C12_Examples/PS2_1c12/PS2.bdf" "" { Schematic "H:/New_file/EP1C12_Examples/PS2_1c12/PS2.bdf" { { 56 248 309 72 "data\[15..8\]" "" } { 72 472 527 88 "data\[7..0\]" "" } { 240 -24 48 256 "data\[15..0\]" "" } { 80 -104 64 96 "data" "" } } } }  } 0 0 "Found inconsistent dimensions for element \"%1!s!\"" 0 0 "" 0 -1}
{ "Warning" "WGDFX_PROCESSING_BUS_NAME_WITH_MAXPLUS_II_NAMING" "data " "Warning: Converted elements in bus name \"data\" using legacy naming rules. Make any assignments on the new names, not on the original names." { { "Warning" "WGDFX_CONVERTING_BUS_NAME" "data\[15..8\] data15..8 " "Warning: Converted element name(s) from \"data\[15..8\]\" to \"data15..8\"" {  } { { "H:/New_file/EP1C12_Examples/PS2_1c12/PS2.bdf" "" { Schematic "H:/New_file/EP1C12_Examples/PS2_1c12/PS2.bdf" { { 56 248 309 72 "data\[15..8\]" "" } } } }  } 0 0 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "" 0 -1} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "data\[7..0\] data7..0 " "Warning: Converted element name(s) from \"data\[7..0\]\" to \"data7..0\"" {  } { { "H:/New_file/EP1C12_Examples/PS2_1c12/PS2.bdf" "" { Schematic "H:/New_file/EP1C12_Examples/PS2_1c12/PS2.bdf" { { 72 472 527 88 "data\[7..0\]" "" } } } }  } 0 0 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "" 0 -1} { "Warning" "WGDFX_CONVERTING_BUS_NAME" "data\[15..0\] data15..0 " "Warning: Converted element name(s) from \"data\[15..0\]\" to \"data15..0\"" {  } { { "H:/New_file/EP1C12_Examples/PS2_1c12/PS2.bdf" "" { Schematic "H:/New_file/EP1C12_Examples/PS2_1c12/PS2.bdf" { { 240 -24 48 256 "data\[15..0\]" "" } } } }  } 0 0 "Converted element name(s) from \"%1!s!\" to \"%2!s!\"" 0 0 "" 0 -1}  } { { "H:/New_file/EP1C12_Examples/PS2_1c12/PS2.bdf" "" { Schematic "H:/New_file/EP1C12_Examples/PS2_1c12/PS2.bdf" { { 56 248 309 72 "data\[15..8\]" "" } { 72 472 527 88 "data\[7..0\]" "" } { 240 -24 48 256 "data\[15..0\]" "" } } } }  } 0 0 "Converted elements in bus name \"%1!s!\" using legacy naming rules. Make any assignments on the new names, not on the original names." 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Create VHDL File 0 s 5 s Quartus II " "Info: Quartus II Create VHDL File was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "165 " "Info: Peak virtual memory: 165 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Sun Apr 19 10:36:55 2009 " "Info: Processing ended: Sun Apr 19 10:36:55 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}