ps2.map.rpt

使用FPGA读取键盘的例子

; segmain.vhd                      ; yes             ; User VHDL File  ; F:/qxc/EP1C12/PS2/segmain.vhd ;
+----------------------------------+-----------------+-----------------+-------------------------------+


+---------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary             ;
+---------------------------------------------+-----------+
; Resource                                    ; Usage     ;
+---------------------------------------------+-----------+
; Total logic elements                        ; 14        ;
;     -- Combinational with no register       ; 12        ;
;     -- Register only                        ; 0         ;
;     -- Combinational with a register        ; 2         ;
;                                             ;           ;
; Logic element usage by number of LUT inputs ;           ;
;     -- 4 input functions                    ; 8         ;
;     -- 3 input functions                    ; 0         ;
;     -- 2 input functions                    ; 5         ;
;     -- 1 input functions                    ; 1         ;
;     -- 0 input functions                    ; 0         ;
;         -- Combinational cells for routing  ; 0         ;
;                                             ;           ;
; Logic elements by mode                      ;           ;
;     -- normal mode                          ; 14        ;
;     -- arithmetic mode                      ; 0         ;
;     -- qfbk mode                            ; 0         ;
;     -- register cascade mode                ; 0         ;
;     -- synchronous clear/load mode          ; 0         ;
;     -- asynchronous clear/load mode         ; 2         ;
;                                             ;           ;
; Total registers                             ; 2         ;
; I/O pins                                    ; 26        ;
; Maximum fan-out node                        ; comclk[0] ;
; Maximum fan-out                             ; 13        ;
; Total fan-out                               ; 55        ;
; Average fan-out                             ; 1.38      ;
+---------------------------------------------+-----------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                    ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
; |segmain                   ; 14 (14)     ; 2            ; 0           ; 26   ; 0            ; 12 (12)      ; 0 (0)             ; 2 (2)            ; 0 (0)           ; 0 (0)      ; |segmain            ;
+----------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 2     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 2     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |segmain|ledcom~3          ;
; 4:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; No         ; |segmain|bcd_led~11        ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in F:/qxc/EP1C12/PS2/PS2.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Fri Apr 14 21:25:23 2006
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off PS2 -c PS2
Info: Assignment "TCL_SCRIPT_FILE" is no longer supported -- removing assignment from Quartus II Settings File
Info: Found 1 design units, including 1 entities, in source file PS2.bdf
    Info: Found entity 1: PS2
Info: Found 2 design units, including 1 entities, in source file data_scanC.vhd
    Info: Found design unit 1: data_scanC-behav
    Info: Found entity 1: data_scanC
Info: Found 2 design units, including 1 entities, in source file convert.vhd
    Info: Found design unit 1: convert-behav
    Info: Found entity 1: convert
Info: Found 2 design units, including 1 entities, in source file mydff.vhd
    Info: Found design unit 1: mydff-SYN
    Info: Found entity 1: mydff
Info: Found 2 design units, including 1 entities, in source file segmain.vhd
    Info: Found design unit 1: segmain-behav
    Info: Found entity 1: segmain
Info: Found 2 design units, including 1 entities, in source file bin27seg.vhd
    Info: Found design unit 1: bin27seg-bin27seg_arch
    Info: Found entity 1: bin27seg
Info: Elaborating entity "segmain" for the top level hierarchy
Warning (10492): VHDL Process Statement warning at segmain.vhd(41): signal "datain" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at segmain.vhd(42): signal "datain" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at segmain.vhd(43): signal "datain" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Warning (10492): VHDL Process Statement warning at segmain.vhd(44): signal "datain" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Implemented 40 device resources after synthesis - the final resource count might be different
    Info: Implemented 18 input pins
    Info: Implemented 8 output pins
    Info: Implemented 14 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
    Info: Processing ended: Fri Apr 14 21:25:27 2006
    Info: Elapsed time: 00:00:05