ps2.vhd

使用FPGA读取键盘的例子

-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files from any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.

-- PROGRAM		"Quartus II"
-- VERSION		"Version 9.0 Build 132 02/25/2009 SJ Web Edition"
-- CREATED ON		"Sun Apr 19 10:38:49 2009"

LIBRARY ieee;
USE ieee.std_logic_1164.all; 

LIBRARY work;

ENTITY PS2 IS 
	PORT
	(
		kbclk :  IN  STD_LOGIC;
		reset :  IN  STD_LOGIC;
		clk :  IN  STD_LOGIC;
		k_data :  IN  STD_LOGIC;
		ledcom :  OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
		seg7 :  OUT  STD_LOGIC_VECTOR(6 DOWNTO 0)
	);
END PS2;

ARCHITECTURE bdf_type OF PS2 IS 

COMPONENT data_scanc
	PORT(sys_clk : IN STD_LOGIC;
		 k_data : IN STD_LOGIC;
		 k_clock : IN STD_LOGIC;
		 reset : IN STD_LOGIC;
		 ZHJS : INOUT STD_LOGIC;
		 PA : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0);
		 data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
	);
END COMPONENT;

COMPONENT convert
	PORT(prepared : IN STD_LOGIC;
		 clr : IN STD_LOGIC;
		 Scan : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
		 data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
	);
END COMPONENT;

COMPONENT bin27seg
	PORT(data_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
		 data_out : OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
	);
END COMPONENT;

COMPONENT lpm_counter0
	PORT(clock : IN STD_LOGIC;
		 q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
	);
END COMPONENT;

COMPONENT segmain
	PORT(clk : IN STD_LOGIC;
		 rst : IN STD_LOGIC;
		 datain : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
		 dataout : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
		 ledcom : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
	);
END COMPONENT;

SIGNAL	data :  STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL	q :  STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL	SYNTHESIZED_WIRE_0 :  STD_LOGIC;
SIGNAL	SYNTHESIZED_WIRE_1 :  STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL	SYNTHESIZED_WIRE_2 :  STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL	SYNTHESIZED_WIRE_3 :  STD_LOGIC;


BEGIN 
SYNTHESIZED_WIRE_3 <= '0';



b2v_inst : data_scanc
PORT MAP(sys_clk => q(0),
		 k_data => k_data,
		 k_clock => kbclk,
		 reset => reset,
		 ZHJS => SYNTHESIZED_WIRE_0,
		 PA => SYNTHESIZED_WIRE_1,
		 data => data(15 DOWNTO 8));


b2v_inst1 : convert
PORT MAP(prepared => SYNTHESIZED_WIRE_0,
		 clr => reset,
		 Scan => SYNTHESIZED_WIRE_1,
		 data => data(7 DOWNTO 0));


b2v_inst3 : bin27seg
PORT MAP(data_in => SYNTHESIZED_WIRE_2,
		 data_out => seg7);


b2v_inst5 : lpm_counter0
PORT MAP(clock => clk,
		 q => q);



b2v_inst9 : segmain
PORT MAP(clk => q(5),
		 rst => SYNTHESIZED_WIRE_3,
		 datain => data,
		 dataout => SYNTHESIZED_WIRE_2,
		 ledcom => ledcom);


END bdf_type;