original_signal.map.qmsg

一种基于LUT的预失真方法。其中的一部分

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Full Version " "Info: Version 7.1 Build 178 06/25/2007 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Nov 25 20:53:13 2007 " "Info: Processing started: Sun Nov 25 20:53:13 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off original_signal -c original_signal " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off original_signal -c original_signal" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FIR/MyCofRom.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file FIR/MyCofRom.v" { { "Info" "ISGN_ENTITY_NAME" "1 MyCofRom " "Info: Found entity 1: MyCofRom" {  } { { "FIR/MyCofRom.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/FIR/MyCofRom.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FIR/FIRInterp.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file FIR/FIRInterp.v" { { "Info" "ISGN_ENTITY_NAME" "1 FIRInterp " "Info: Found entity 1: FIRInterp" {  } { { "FIR/FIRInterp.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/FIR/FIRInterp.v" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CICsilu.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file CICsilu.v" { { "Info" "ISGN_ENTITY_NAME" "1 CICsilu " "Info: Found entity 1: CICsilu" {  } { { "CICsilu.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/CICsilu.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "OFDMrom.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file OFDMrom.v" { { "Info" "ISGN_ENTITY_NAME" "1 OFDMrom " "Info: Found entity 1: OFDMrom" {  } { { "OFDMrom.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/OFDMrom.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "datarom.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file datarom.v" { { "Info" "ISGN_ENTITY_NAME" "1 datarom " "Info: Found entity 1: datarom" {  } { { "datarom.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/datarom.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "HBFirCof.V 2 2 " "Info: Found 2 design units, including 2 entities, in source file HBFirCof.V" { { "Info" "ISGN_ENTITY_NAME" "1 HBFirCof_1 " "Info: Found entity 1: HBFirCof_1" {  } { { "HBFirCof.V" "" { Text "E:/Graduation_Design/Quartus/original_signal/HBFirCof.V" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 HBFirCof_2 " "Info: Found entity 2: HBFirCof_2" {  } { { "HBFirCof.V" "" { Text "E:/Graduation_Design/Quartus/original_signal/HBFirCof.V" 29 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FIRHB.v 3 3 " "Info: Found 3 design units, including 3 entities, in source file FIRHB.v" { { "Info" "ISGN_ENTITY_NAME" "1 FIRHB " "Info: Found entity 1: FIRHB" {  } { { "FIRHB.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/FIRHB.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 ram_Buff1 " "Info: Found entity 2: ram_Buff1" {  } { { "FIRHB.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/FIRHB.v" 96 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "3 ram_Buff2 " "Info: Found entity 3: ram_Buff2" {  } { { "FIRHB.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/FIRHB.v" 111 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CLK_ALL_GEN.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file CLK_ALL_GEN.v" { { "Info" "ISGN_ENTITY_NAME" "1 CLK_ALL_GEN " "Info: Found entity 1: CLK_ALL_GEN" {  } { { "CLK_ALL_GEN.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/CLK_ALL_GEN.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ROMDataTable.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ROMDataTable.v" { { "Info" "ISGN_ENTITY_NAME" "1 ROMDataTable " "Info: Found entity 1: ROMDataTable" {  } { { "ROMDataTable.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/ROMDataTable.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CICnew.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file CICnew.v" { { "Info" "ISGN_ENTITY_NAME" "1 CICnew " "Info: Found entity 1: CICnew" {  } { { "CICnew.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/CICnew.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DABDataOut.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file DABDataOut.v" { { "Info" "ISGN_ENTITY_NAME" "1 DABDataOut " "Info: Found entity 1: DABDataOut" {  } { { "DABDataOut.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/DABDataOut.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DATAW dataw dds2ch.v(707) " "Info (10281): Verilog HDL Declaration information at dds2ch.v(707): object \"DATAW\" differs only in case from object \"dataw\" in the same scope" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 707 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "" 0}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DATAC datac dds2ch.v(708) " "Info (10281): Verilog HDL Declaration information at dds2ch.v(708): object \"DATAC\" differs only in case from object \"datac\" in the same scope" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 708 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "" 0}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "W1 w1 dds2ch.v(934) " "Info (10281): Verilog HDL Declaration information at dds2ch.v(934): object \"W1\" differs only in case from object \"w1\" in the same scope" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 934 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "" 0}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "W2 w2 dds2ch.v(934) " "Info (10281): Verilog HDL Declaration information at dds2ch.v(934): object \"W2\" differs only in case from object \"w2\" in the same scope" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 934 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "" 0}
{ "Warning" "WSGN_MEGAFN_REPLACE" "mux E:/Graduation_Design/Quartus/original_signal/dds2ch.v " "Warning: Entity \"mux\" obtained from \"E:/Graduation_Design/Quartus/original_signal/dds2ch.v\" instead of from Quartus II megafunction library" {  } {  } 0 0 "Entity \"%1!s!\" obtained from \"%2!s!\" instead of from Quartus II megafunction library" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dds2ch.v 14 14 " "Info: Found 14 design units, including 14 entities, in source file dds2ch.v" { { "Info" "ISGN_ENTITY_NAME" "1 dds2ch " "Info: Found entity 1: dds2ch" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 21 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "2 accl " "Info: Found entity 2: accl" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 164 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "3 bctrl " "Info: Found entity 3: bctrl" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 262 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "4 inverter " "Info: Found entity 4: inverter" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 334 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "5 romcl " "Info: Found entity 5: romcl" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 375 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "6 romwl " "Info: Found entity 6: romwl" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 532 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "7 mux " "Info: Found entity 7: mux" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 689 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "8 muad " "Info: Found entity 8: muad" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 768 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "9 delayl " "Info: Found entity 9: delayl" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 912 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "10 out " "Info: Found entity 10: out" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 994 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "11 mult " "Info: Found entity 11: mult" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 1114 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "12 add " "Info: Found entity 12: add" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 1144 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "13 sub " "Info: Found entity 13: sub" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 1172 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "14 addo " "Info: Found entity 14: addo" {  } { { "dds2ch.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/dds2ch.v" 1199 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "frecontr.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file frecontr.v" { { "Info" "ISGN_ENTITY_NAME" "1 frecontr " "Info: Found entity 1: frecontr" {  } { { "frecontr.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/frecontr.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0 "" 0}