📄 original_signal.hif

📁 一种基于LUT的预失真方法。其中的一部分
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PARAMETER_UNKNOWN
USR
PORT_CLKENA4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKENA5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLKENA0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA2
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLKENA3
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_EXTCLK0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_EXTCLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD0
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKBAD1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_CLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK2
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK3
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK4
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK5
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLK6
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK7
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK8
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_CLK9
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCANDATA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDATAOUT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCLKOUT1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_SCLKOUT0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ACTIVECLOCK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKLOSS
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK1
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_INCLK0
PORT_USED
PARAMETER_UNKNOWN
USR
PORT_FBIN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PLLENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CLKSWITCH
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ARESET
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PFDENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLK
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANACLR
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANREAD
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANWRITE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_ENABLE0
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_ENABLE1
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_LOCKED
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_CONFIGUPDATE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_FBOUT
PORT_CONNECTIVITY
PARAMETER_UNKNOWN
DEF
PORT_PHASEDONE
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASESTEP
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASEUPDOWN
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_SCANCLKENA
PORT_UNUSED
PARAMETER_UNKNOWN
USR
PORT_PHASECOUNTERSELECT
PORT_UNUSED
PARAMETER_UNKNOWN
USR
M_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C0_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C1_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C2_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C3_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C4_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C5_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C6_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C7_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C8_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
C9_TEST_SOURCE
5
PARAMETER_UNKNOWN
DEF
CBXI_PARAMETER
altpll_7f31
PARAMETER_UNKNOWN
USR
VCO_FREQUENCY_CONTROL
AUTO
PARAMETER_UNKNOWN
DEF
VCO_PHASE_SHIFT_STEP
0
PARAMETER_UNKNOWN
DEF
WIDTH_CLOCK
5
PARAMETER_SIGNED_DEC
USR
WIDTH_PHASECOUNTERSELECT
4
PARAMETER_UNKNOWN
DEF
USING_FBMIMICBIDIR_PORT
OFF
PARAMETER_UNKNOWN
DEF
DEVICE_FAMILY
Cyclone III
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
inclk
-1
3
clk
-1
3
scanwrite
-1
1
scanread
-1
1
scandata
-1
1
scanclk
-1
1
scanaclr
-1
1
clkswitch
-1
1
areset
-1
1
scanclkena
-1
2
pllena
-1
2
phaseupdown
-1
2
phasestep
-1
2
phasecounterselect
-1
2
pfdena
-1
2
fbin
-1
2
extclkena
-1
2
configupdate
-1
2
clkena
-1
2
}
# include_file {
c:|altera|71|quartus|libraries|megafunctions|aglobal71.inc
80b63f71158cd1a01acf29ef94ccd6
c:|altera|71|quartus|libraries|megafunctions|stratix_pll.inc
5f8211898149ceae8264a0ea5036254f
c:|altera|71|quartus|libraries|megafunctions|stratixii_pll.inc
6d1985e16ab5f59a1fd6b0ae20978a4e
c:|altera|71|quartus|libraries|megafunctions|cycloneii_pll.inc
39a0d9d1237d1db39c848c3f9faffc
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
altpll_7f31
# storage
db|original_signal.(4).cnf
db|original_signal.(4).cnf
# case_insensitive
# source_file
db|altpll_7f31.tdf
24e223137a10c54a9e4cea09d8a57b1
6
# user_parameter {
CLKOUT_WIDTH
5
PARAMETER_UNKNOWN
DEF
PHASECOUNTERSELECT_WIDTH
3
PARAMETER_UNKNOWN
DEF
}
# used_port {
inclk1
-1
3
inclk0
-1
3
clk4
-1
3
clk3
-1
3
clk2
-1
3
clk1
-1
3
clk0
-1
3
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
ROMDataTable
# storage
db|original_signal.(7).cnf
db|original_signal.(7).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
ROMDataTable.v
19da5793c12cf7c7e727c4f151b5e66
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
dds2ch
# storage
db|original_signal.(9).cnf
db|original_signal.(9).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
dds2ch.v
4aab194382f91bc0cd5b6f6fbf4a4bf
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
FREQ_BITS
32
PARAMETER_UNKNOWN
USR
DATA_BITS
14
PARAMETER_UNKNOWN
USR
U_BITS
17
PARAMETER_UNKNOWN
USR
ADDR_M
7
PARAMETER_UNKNOWN
USR
ADDR_N
7
PARAMETER_UNKNOWN
USR
WAVE_BITS
13
PARAMETER_UNKNOWN
USR
COEFF_BITS
8
PARAMETER_UNKNOWN
USR
INTER_BITS
7
PARAMETER_UNKNOWN
USR
}
# hierarchies {
dds2ch:inst3
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
accl
# storage
db|original_signal.(10).cnf
db|original_signal.(10).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
dds2ch.v
4aab194382f91bc0cd5b6f6fbf4a4bf
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
FREQ_BITS
32
PARAMETER_SIGNED_DEC
USR
U_BITS
17
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
dds2ch:inst3|accl:U_accl
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
bctrl
# storage
db|original_signal.(11).cnf
db|original_signal.(11).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
dds2ch.v
4aab194382f91bc0cd5b6f6fbf4a4bf
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
U_BITS
17
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
dds2ch:inst3|bctrl:U_bctrl
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
inverter
# storage
db|original_signal.(12).cnf
db|original_signal.(12).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
dds2ch.v
4aab194382f91bc0cd5b6f6fbf4a4bf
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
U_BITS
17
PARAMETER_SIGNED_DEC
USR
ADDR_M
7
PARAMETER_SIGNED_DEC
USR
ADDR_N
7
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
dds2ch:inst3|inverter:U_inverter
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
romwl
# storage
db|original_signal.(13).cnf
db|original_signal.(13).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
dds2ch.v
4aab194382f91bc0cd5b6f6fbf4a4bf
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
ROM_BITS
7
PARAMETER_SIGNED_DEC
USR
WAVE_BITS
13
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
dds2ch:inst3|romwl:U_romwl
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
romcl
# storage
db|original_signal.(14).cnf
db|original_signal.(14).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
dds2ch.v
4aab194382f91bc0cd5b6f6fbf4a4bf
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
ROM_BITS
7
PARAMETER_SIGNED_DEC
USR
COEFF_BITS
8
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
dds2ch:inst3|romcl:U_romcl
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
mux
# storage
db|original_signal.(15).cnf
db|original_signal.(15).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
dds2ch.v
4aab194382f91bc0cd5b6f6fbf4a4bf
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
WAVE_BITS
13
PARAMETER_SIGNED_DEC
USR
COEFF_BITS
8
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
dds2ch:inst3|mux:U_mux
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
muad
# storage
db|original_signal.(16).cnf
db|original_signal.(16).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
dds2ch.v
4aab194382f91bc0cd5b6f6fbf4a4bf
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
WAVE_BITS
13
PARAMETER_SIGNED_DEC
USR
COEFF_BITS
8
PARAMETER_SIGNED_DEC
USR
INTER_BITS
7
PARAMETER_SIGNED_DEC
USR
ADDR_N
7
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
dds2ch:inst3|muad:U_muad
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
add
# storage
db|original_signal.(17).cnf
db|original_signal.(17).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
dds2ch.v
4aab194382f91bc0cd5b6f6fbf4a4bf
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
dds2ch:inst3|muad:U_muad|add:U_add
dds2ch:inst3|muad:U_muad|add:U1_add
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
sub
# storage
db|original_signal.(18).cnf
db|original_signal.(18).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
dds2ch.v
4aab194382f91bc0cd5b6f6fbf4a4bf
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
dds2ch:inst3|muad:U_muad|sub:U_sub
dds2ch:inst3|muad:U_muad|sub:U1_sub
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
mult
# storage
db|original_signal.(19).cnf
db|original_signal.(19).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
dds2ch.v
4aab194382f91bc0cd5b6f6fbf4a4bf
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
dds2ch:inst3|muad:U_muad|mult:U_mult
dds2ch:inst3|muad:U_muad|mult:U1_mult
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
delayl
# storage
db|original_signal.(20).cnf
db|original_signal.(20).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
dds2ch.v
4aab194382f91bc0cd5b6f6fbf4a4bf
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
WAVE_BITS
13
PARAMETER_SIGNED_DEC
USR
COEFF_BITS
8
PARAMETER_SIGNED_DEC
USR
INTER_BITS
7
PARAMETER_SIGNED_DEC
USR
ADDR_N
7
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
dds2ch:inst3|muad:U_muad|delayl:U_delayl
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
out
# storage
db|original_signal.(21).cnf
db|original_signal.(21).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
dds2ch.v
4aab194382f91bc0cd5b6f6fbf4a4bf
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
WAVE_BITS
13
PARAMETER_SIGNED_DEC
USR
}
# hierarchies {
dds2ch:inst3|out:U_out
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
addo
# storage
db|original_signal.(22).cnf
db|original_signal.(22).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
dds2ch.v
4aab194382f91bc0cd5b6f6fbf4a4bf
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# hierarchies {
dds2ch:inst3|out:U_out|addo:U_addo
dds2ch:inst3|out:U_out|addo:U1_addo
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
frecontr
# storage
db|original_signal.(23).cnf
db|original_signal.(23).cnf
# logic_option {
AUTO_RAM_RECOGNITION
ON
}
# case_sensitive
# source_file
frecontr.v
341c6acfd2625cb8aa8454740e59ded
7
# internal_option {
HDL_INITIAL_FANOUT_LIMIT
OFF
AUTO_RESOURCE_SHARING
OFF
AUTO_RAM_RECOGNITION
ON
AUTO_ROM_RECOGNITION
ON
IGNORE_VERILOG_INITIAL_CONSTRUCTS
OFF
}
# user_parameter {
FREQ_BITS
32
PARAMETER_UNKNOWN
USR
}
# hierarchies {
frecontr:inst2
}
# lmf
c:|altera|71|quartus|lmf|
d41d8cd98f0b24e980998ecf8427e
# macro_sequence

# end
# entity
altsyncram
# storage
db|original_signal.(24).cnf
db|original_signal.(24).cnf
# case_insensitive
# source_file
c:|altera|71|quartus|libraries|megafunctions|altsyncram.tdf
3d41d911345144598dd1e0fb6bf98d
6
# user_parameter {
BYTE_SIZE_BLOCK
8
PARAMETER_UNKNOWN
DEF
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
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