original_signal.fit.qmsg

来自「一种基于LUT的预失真方法。其中的一部分」· QMSG 代码 · 共 37 行 · 第 1/5 页

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "1 6 " "Info: Average interconnect usage is 1% of the available device resources. Peak interconnect usage is 6%" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "X32_Y11 X42_Y22 " "Info: The peak interconnect region extends from location X32_Y11 to location X42_Y22" {  } {  } 0 0 "The peak interconnect region extends from location %1!s! to location %2!s!" 0 0 "" 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources. Peak interconnect usage is %2!d!%%" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Info: Fitter routing operations ending: elapsed time is 00:00:02" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0}
{ "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_MAIN_TITLE" "1 " "Info: Fitter merged 1 physical RAM blocks that contain multiple logical RAM slices into a single location" { { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_TITLE" "" "Info: Following physical RAM blocks contain multiple logical RAM slices" { { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_PHYSICAL_LOCATION" "M9K_X22_Y21_N0 " "Info: Physical RAM block M9K_X22_Y21_N0 contains the following logical RAM slices" { { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "dds2ch:inst3\|romcl:U_romcl\|altsyncram:Ram0_rtl_2\|altsyncram_guv:auto_generated\|ram_block1a0 " "Info: RAM slice: dds2ch:inst3\|romcl:U_romcl\|altsyncram:Ram0_rtl_2\|altsyncram_guv:auto_generated\|ram_block1a0" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "dds2ch:inst3\|romcl:U_romcl\|altsyncram:Ram0_rtl_2\|altsyncram_guv:auto_generated\|ram_block1a1 " "Info: RAM slice: dds2ch:inst3\|romcl:U_romcl\|altsyncram:Ram0_rtl_2\|altsyncram_guv:auto_generated\|ram_block1a1" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "dds2ch:inst3\|romcl:U_romcl\|altsyncram:Ram0_rtl_2\|altsyncram_guv:auto_generated\|ram_block1a2 " "Info: RAM slice: dds2ch:inst3\|romcl:U_romcl\|altsyncram:Ram0_rtl_2\|altsyncram_guv:auto_generated\|ram_block1a2" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "dds2ch:inst3\|romcl:U_romcl\|altsyncram:Ram0_rtl_2\|altsyncram_guv:auto_generated\|ram_block1a3 " "Info: RAM slice: dds2ch:inst3\|romcl:U_romcl\|altsyncram:Ram0_rtl_2\|altsyncram_guv:auto_generated\|ram_block1a3" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "dds2ch:inst3\|romcl:U_romcl\|altsyncram:Ram0_rtl_2\|altsyncram_guv:auto_generated\|ram_block1a4 " "Info: RAM slice: dds2ch:inst3\|romcl:U_romcl\|altsyncram:Ram0_rtl_2\|altsyncram_guv:auto_generated\|ram_block1a4" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "dds2ch:inst3\|romcl:U_romcl\|altsyncram:Ram0_rtl_2\|altsyncram_guv:auto_generated\|ram_block1a8 " "Info: RAM slice: dds2ch:inst3\|romcl:U_romcl\|altsyncram:Ram0_rtl_2\|altsyncram_guv:auto_generated\|ram_block1a8" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "dds2ch:inst3\|romcl:U_romcl\|altsyncram:Ram0_rtl_2\|altsyncram_guv:auto_generated\|ram_block1a9 " "Info: RAM slice: dds2ch:inst3\|romcl:U_romcl\|altsyncram:Ram0_rtl_2\|altsyncram_guv:auto_generated\|ram_block1a9" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "dds2ch:inst3\|romcl:U_romcl\|altsyncram:Ram0_rtl_2\|altsyncram_guv:auto_generated\|ram_block1a10 " "Info: RAM slice: dds2ch:inst3\|romcl:U_romcl\|altsyncram:Ram0_rtl_2\|altsyncram_guv:auto_generated\|ram_block1a10" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "dds2ch:inst3\|romcl:U_romcl\|altsyncram:Ram0_rtl_2\|altsyncram_guv:auto_generated\|ram_block1a11 " "Info: RAM slice: dds2ch:inst3\|romcl:U_romcl\|altsyncram:Ram0_rtl_2\|altsyncram_guv:auto_generated\|ram_block1a11" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "dds2ch:inst3\|romcl:U_romcl\|altsyncram:Ram0_rtl_2\|altsyncram_guv:auto_generated\|ram_block1a12 " "Info: RAM slice: dds2ch:inst3\|romcl:U_romcl\|altsyncram:Ram0_rtl_2\|altsyncram_guv:auto_generated\|ram_block1a12" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "dds2ch:inst3\|romwl:U_romwl\|altsyncram:Ram0_rtl_1\|altsyncram_mtv:auto_generated\|ram_block1a0 " "Info: RAM slice: dds2ch:inst3\|romwl:U_romwl\|altsyncram:Ram0_rtl_1\|altsyncram_mtv:auto_generated\|ram_block1a0" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "dds2ch:inst3\|romwl:U_romwl\|altsyncram:Ram0_rtl_1\|altsyncram_mtv:auto_generated\|ram_block1a1 " "Info: RAM slice: dds2ch:inst3\|romwl:U_romwl\|altsyncram:Ram0_rtl_1\|altsyncram_mtv:auto_generated\|ram_block1a1" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "dds2ch:inst3\|romwl:U_romwl\|altsyncram:Ram0_rtl_1\|altsyncram_mtv:auto_generated\|ram_block1a2 " "Info: RAM slice: dds2ch:inst3\|romwl:U_romwl\|altsyncram:Ram0_rtl_1\|altsyncram_mtv:auto_generated\|ram_block1a2" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "dds2ch:inst3\|romwl:U_romwl\|altsyncram:Ram0_rtl_1\|altsyncram_mtv:auto_generated\|ram_block1a3 " "Info: RAM slice: dds2ch:inst3\|romwl:U_romwl\|altsyncram:Ram0_rtl_1\|altsyncram_mtv:auto_generated\|ram_block1a3" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "dds2ch:inst3\|romwl:U_romwl\|altsyncram:Ram0_rtl_1\|altsyncram_mtv:auto_generated\|ram_block1a4 " "Info: RAM slice: dds2ch:inst3\|romwl:U_romwl\|altsyncram:Ram0_rtl_1\|altsyncram_mtv:auto_generated\|ram_block1a4" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "dds2ch:inst3\|romwl:U_romwl\|altsyncram:Ram0_rtl_1\|altsyncram_mtv:auto_generated\|ram_block1a5 " "Info: RAM slice: dds2ch:inst3\|romwl:U_romwl\|altsyncram:Ram0_rtl_1\|altsyncram_mtv:auto_generated\|ram_block1a5" {  } {  } 2 0 "RAM slice: %1!s!" 0 0 "" 0} { "Info" "IFSAC_MULTIPLE_LOGICAL_RAMS_MERGED_SUB_MSG_SLICE_NAME" "dds2ch:inst3\|romwl:U_romwl\|altsyncram:Ram0_rtl_1\|altsyncram_mtv:auto_generated\|ram_block1a6 " "Info: RAM slice: dds2ch:inst3\|romwl:U_romwl\|altsyncram:Ram0_rtl_1\|altsyncram_mtv:auto_generated\|ram_block1a6" {  } {  } 2 0 "RAM slice: %