prev_cmp_original_signal.tan.qmsg

来自「一种基于LUT的预失真方法。其中的一部分」· QMSG 代码 · 共 10 行 · 第 1/5 页

{ "Info" "ITAN_NO_REG2REG_EXIST" "clkin " "Info: No valid register-to-register data paths exist for clock \"clkin\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] register datarom:inst\|add\[1\] memory datarom:inst\|OFDMrom_center_167:myrom\|altsyncram:Ram0_rtl_4\|altsyncram_g511:auto_generated\|ram_block1a14~porta_address_reg1 620 ps " "Info: Minimum slack time is 620 ps for clock \"altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]\" between source register \"datarom:inst\|add\[1\]\" and destination memory \"datarom:inst\|OFDMrom_center_167:myrom\|altsyncram:Ram0_rtl_4\|altsyncram_g511:auto_generated\|ram_block1a14~porta_address_reg1\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.025 ns + Shortest register memory " "Info: + Shortest register to memory delay is 1.025 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns datarom:inst\|add\[1\] 1 REG FF_X23_Y8_N3 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = FF_X23_Y8_N3; Fanout = 10; REG Node = 'datarom:inst\|add\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { datarom:inst|add[1] } "NODE_NAME" } } { "datarom.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/datarom.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.938 ns) + CELL(0.087 ns) 1.025 ns datarom:inst\|OFDMrom_center_167:myrom\|altsyncram:Ram0_rtl_4\|altsyncram_g511:auto_generated\|ram_block1a14~porta_address_reg1 2 MEM M9K_X22_Y8_N0 4 " "Info: 2: + IC(0.938 ns) + CELL(0.087 ns) = 1.025 ns; Loc. = M9K_X22_Y8_N0; Fanout = 4; MEM Node = 'datarom:inst\|OFDMrom_center_167:myrom\|altsyncram:Ram0_rtl_4\|altsyncram_g511:auto_generated\|ram_block1a14~porta_address_reg1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.025 ns" { datarom:inst|add[1] datarom:inst|OFDMrom_center_167:myrom|altsyncram:Ram0_rtl_4|altsyncram_g511:auto_generated|ram_block1a14~porta_address_reg1 } "NODE_NAME" } } { "db/altsyncram_g511.tdf" "" { Text "E:/Graduation_Design/Quartus/original_signal/db/altsyncram_g511.tdf" 323 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.087 ns ( 8.49 % ) " "Info: Total cell delay = 0.087 ns ( 8.49 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.938 ns ( 91.51 % ) " "Info: Total interconnect delay = 0.938 ns ( 91.51 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.025 ns" { datarom:inst|add[1] datarom:inst|OFDMrom_center_167:myrom|altsyncram:Ram0_rtl_4|altsyncram_g511:auto_generated|ram_block1a14~porta_address_reg1 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "1.025 ns" { datarom:inst|add[1] datarom:inst|OFDMrom_center_167:myrom|altsyncram:Ram0_rtl_4|altsyncram_g511:auto_generated|ram_block1a14~porta_address_reg1 } { 0.000ns 0.938ns } { 0.000ns 0.087ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "0.405 ns - Smallest register memory " "Info: - Smallest register to memory requirement is 0.405 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -3.874 ns " "Info: + Latch edge is -3.874 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] 15.254 ns -3.874 ns  50 " "Info: Clock period of Destination clock \"altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]\" is 15.254 ns with  offset of -3.874 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -3.874 ns " "Info: - Launch edge is -3.874 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] 15.254 ns -3.874 ns  50 " "Info: Clock period of Source clock \"altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]\" is 15.254 ns with  offset of -3.874 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0}  } {  } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.428 ns + Smallest " "Info: + Smallest clock skew is 0.428 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] destination 8.879 ns + Longest memory " "Info: + Longest clock path from clock \"altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]\" to destination memory is 8.879 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] } "NODE_NAME" } } { "db/altpll_ena1.tdf" "" { Text "E:/Graduation_Design/Quartus/original_signal/db/altpll_ena1.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.393 ns) + CELL(0.000 ns) 2.393 ns altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]~clkctrl 2 COMB CLKCTRL_G3 834 " "Info: 2: + IC(2.393 ns) + CELL(0.000 ns) = 2.393 ns; Loc. = CLKCTRL_G3; Fanout = 834; COMB Node = 'altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.393 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl } "NODE_NAME" } } { "db/altpll_ena1.tdf" "" { Text "E:/Graduation_Design/Quartus/original_signal/db/altpll_ena1.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.246 ns) + CELL(0.969 ns) 4.608 ns CLK_ALL_GEN:inst5\|count\[4\] 3 REG FF_X35_Y17_N15 44 " "Info: 3: + IC(1.246 ns) + CELL(0.969 ns) = 4.608 ns; Loc. = FF_X35_Y17_N15; Fanout = 44; REG Node = 'CLK_ALL_GEN:inst5\|count\[4\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.215 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[4] } "NODE_NAME" } } { "CLK_ALL_GEN.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/CLK_ALL_GEN.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.922 ns) + CELL(0.000 ns) 6.530 ns CLK_ALL_GEN:inst5\|count\[4\]~clkctrl 4 COMB CLKCTRL_G5 107 " "Info: 4: + IC(1.922 ns) + CELL(0.000 ns) = 6.530 ns; Loc. = CLKCTRL_G5; Fanout = 107; COMB Node = 'CLK_ALL_GEN:inst5\|count\[4\]~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.922 ns" { CLK_ALL_GEN:inst5|count[4] CLK_ALL_GEN:inst5|count[4]~clkctrl } "NODE_NAME" } } { "CLK_ALL_GEN.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/CLK_ALL_GEN.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.231 ns) + CELL(1.118 ns) 8.879 ns datarom:inst\|OFDMrom_center_167:myrom\|altsyncram:Ram0_rtl_4\|altsyncram_g511:auto_generated\|ram_block1a14~porta_address_reg1 5 MEM M9K_X22_Y8_N0 4 " "Info: 5: + IC(1.231 ns) + CELL(1.118 ns) = 8.879 ns; Loc. = M9K_X22_Y8_N0; Fanout = 4; MEM Node = 'datarom:inst\|OFDMrom_center_167:myrom\|altsyncram:Ram0_rtl_4\|altsyncram_g511:auto_generated\|ram_block1a14~porta_address_reg1'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.349 ns" { CLK_ALL_GEN:inst5|count[4]~clkctrl datarom:inst|OFDMrom_center_167:myrom|altsyncram:Ram0_rtl_4|altsyncram_g511:auto_generated|ram_block1a14~porta_address_reg1 } "NODE_NAME" } } { "db/altsyncram_g511.tdf" "" { Text "E:/Graduation_Design/Quartus/original_signal/db/altsyncram_g511.tdf" 323 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.087 ns ( 23.50 % ) " "Info: Total cell delay = 2.087 ns ( 23.50 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.792 ns ( 76.50 % ) " "Info: Total interconnect delay = 6.792 ns ( 76.50 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.879 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[4] CLK_ALL_GEN:inst5|count[4]~clkctrl datarom:inst|OFDMrom_center_167:myrom|altsyncram:Ram0_rtl_4|altsyncram_g511:auto_generated|ram_block1a14~porta_address_reg1 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.879 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[4] CLK_ALL_GEN:inst5|count[4]~clkctrl datarom:inst|OFDMrom_center_167:myrom|altsyncram:Ram0_rtl_4|altsyncram_g511:auto_generated|ram_block1a14~porta_address_reg1 } { 0.000ns 2.393ns 1.246ns 1.922ns 1.231ns } { 0.000ns 0.000ns 0.969ns 0.000ns 1.118ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] source 8.451 ns - Shortest register " "Info: - Shortest clock path from clock \"altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]\" to source register is 8.451 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\] 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] } "NODE_NAME" } } { "db/altpll_ena1.tdf" "" { Text "E:/Graduation_Design/Quartus/original_signal/db/altpll_ena1.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.393 ns) + CELL(0.000 ns) 2.393 ns altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]~clkctrl 2 COMB CLKCTRL_G3 834 " "Info: 2: + IC(2.393 ns) + CELL(0.000 ns) = 2.393 ns; Loc. = CLKCTRL_G3; Fanout = 834; COMB Node = 'altpll0:inst6\|altpll:altpll_component\|altpll_ena1:auto_generated\|clk\[0\]~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.393 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl } "NODE_NAME" } } { "db/altpll_ena1.tdf" "" { Text "E:/Graduation_Design/Quartus/original_signal/db/altpll_ena1.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.246 ns) + CELL(0.969 ns) 4.608 ns CLK_ALL_GEN:inst5\|count\[4\] 3 REG FF_X35_Y17_N15 44 " "Info: 3: + IC(1.246 ns) + CELL(0.969 ns) = 4.608 ns; Loc. = FF_X35_Y17_N15; Fanout = 44; REG Node = 'CLK_ALL_GEN:inst5\|count\[4\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.215 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[4] } "NODE_NAME" } } { "CLK_ALL_GEN.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/CLK_ALL_GEN.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.922 ns) + CELL(0.000 ns) 6.530 ns CLK_ALL_GEN:inst5\|count\[4\]~clkctrl 4 COMB CLKCTRL_G5 107 " "Info: 4: + IC(1.922 ns) + CELL(0.000 ns) = 6.530 ns; Loc. = CLKCTRL_G5; Fanout = 107; COMB Node = 'CLK_ALL_GEN:inst5\|count\[4\]~clkctrl'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.922 ns" { CLK_ALL_GEN:inst5|count[4] CLK_ALL_GEN:inst5|count[4]~clkctrl } "NODE_NAME" } } { "CLK_ALL_GEN.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/CLK_ALL_GEN.v" 33 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.231 ns) + CELL(0.690 ns) 8.451 ns datarom:inst\|add\[1\] 5 REG FF_X23_Y8_N3 10 " "Info: 5: + IC(1.231 ns) + CELL(0.690 ns) = 8.451 ns; Loc. = FF_X23_Y8_N3; Fanout = 10; REG Node = 'datarom:inst\|add\[1\]'" {  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.921 ns" { CLK_ALL_GEN:inst5|count[4]~clkctrl datarom:inst|add[1] } "NODE_NAME" } } { "datarom.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/datarom.v" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.659 ns ( 19.63 % ) " "Info: Total cell delay = 1.659 ns ( 19.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.792 ns ( 80.37 % ) " "Info: Total interconnect delay = 6.792 ns ( 80.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.451 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[4] CLK_ALL_GEN:inst5|count[4]~clkctrl datarom:inst|add[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.451 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[4] CLK_ALL_GEN:inst5|count[4]~clkctrl datarom:inst|add[1] } { 0.000ns 2.393ns 1.246ns 1.922ns 1.231ns } { 0.000ns 0.000ns 0.969ns 0.000ns 0.690ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.879 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[4] CLK_ALL_GEN:inst5|count[4]~clkctrl datarom:inst|OFDMrom_center_167:myrom|altsyncram:Ram0_rtl_4|altsyncram_g511:auto_generated|ram_block1a14~porta_address_reg1 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.879 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[4] CLK_ALL_GEN:inst5|count[4]~clkctrl datarom:inst|OFDMrom_center_167:myrom|altsyncram:Ram0_rtl_4|altsyncram_g511:auto_generated|ram_block1a14~porta_address_reg1 } { 0.000ns 2.393ns 1.246ns 1.922ns 1.231ns } { 0.000ns 0.000ns 0.969ns 0.000ns 1.118ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.451 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[4] CLK_ALL_GEN:inst5|count[4]~clkctrl datarom:inst|add[1] } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.451 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[4] CLK_ALL_GEN:inst5|count[4]~clkctrl datarom:inst|add[1] } { 0.000ns 2.393ns 1.246ns 1.922ns 1.231ns } { 0.000ns 0.000ns 0.969ns 0.000ns 0.690ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.279 ns - " "Info: - Micro clock to output delay of source is 0.279 ns" {  } { { "datarom.v" "" { Text "E:/Graduation_Design/Quartus/original_signal/datarom.v" 12 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.256 ns + " "Info: + Micro hold delay of destination is 0.256 ns" {  } { { "db/altsyncram_g511.tdf" "" { Text "E:/Graduation_Design/Quartus/original_signal/db/altsyncram_g511.tdf" 323 2 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0}  } { { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.879 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[4] CLK_ALL_GEN:inst5|count[4]~clkctrl datarom:inst|OFDMrom_center_167:myrom|altsyncram:Ram0_rtl_4|altsyncram_g511:auto_generated|ram_block1a14~porta_address_reg1 } "NODE_NAME" } } { "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.879 ns" { altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0] altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]~clkctrl CLK_ALL_GEN:inst5|count[4] CLK_ALL_GEN:inst5|count[4]~clkctrl datarom:inst|OFDMrom_center_167:myrom|altsyncram:Ram0_rtl_4|altsyncram_g511:auto_generated|ram_block1a14~porta_address_reg1 } { 0.000ns 2.393ns 1.246ns 1.922ns 1.231ns } { 0.000ns 0.000ns 0.969ns 0.000ns 1.118ns } "" } } { "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.451 ns" { altpll0:inst6|altpll:altpll_component|