original_signal.fit.rpt

一种基于LUT的预失真方法。其中的一部分

;     Dedicated logic registers      ; 573 / 24,624 ( 2 % )                          ;
; Total registers                    ; 573                                           ;
; Total pins                         ; 15 / 149 ( 10 % )                             ;
; Total virtual pins                 ; 0                                             ;
; Total memory bits                  ; 76,032 / 608,256 ( 13 % )                     ;
; Embedded Multiplier 9-bit elements ; 6 / 132 ( 5 % )                               ;
; Total PLLs                         ; 1 / 4 ( 25 % )                                ;
+------------------------------------+-----------------------------------------------+


+-----------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings                                                                                                                         ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option                                                                ; Setting                        ; Default Value                  ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device                                                                ; EP3C25Q240C8                   ;                                ;
; Fit Attempts to Skip                                                  ; 0                              ; 0.0                            ;
; Use TimeQuest Timing Analyzer                                         ; Off                            ;                                ;
; Router Timing Optimization Level                                      ; Normal                         ; Normal                         ;
; Placement Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Router Effort Multiplier                                              ; 1.0                            ; 1.0                            ;
; Optimize Hold Timing                                                  ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                           ; Off                            ; Off                            ;
; PowerPlay Power Optimization                                          ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                       ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                            ; On                             ; On                             ;
; Limit to One Fitting Attempt                                          ; Off                            ; Off                            ;
; Final Placement Optimizations                                         ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                           ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                         ; 1                              ; 1                              ;
; PCI I/O                                                               ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                                 ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                             ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                    ; Off                            ; Off                            ;
; Auto Packed Registers -- Stratix II/II GX/III Cyclone II/III Arria GX ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                     ; On                             ; On                             ;
; Auto Merge PLLs                                                       ; On                             ; On                             ;
; Perform Physical Synthesis for Combinational Logic for Fitting        ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance    ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                          ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                           ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                             ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                                ; Off                            ; Off                            ;
; Fitter Effort                                                         ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                       ; Normal                         ; Normal                         ;
; Logic Cell Insertion - Logic Duplication                              ; Auto                           ; Auto                           ;
; Auto Register Duplication                                             ; Auto                           ; Auto                           ;
; Auto Global Clock                                                     ; On                             ; On                             ;
; Auto Global Register Control Signals                                  ; On                             ; On                             ;
; Stop After Congestion Map Generation                                  ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                     ; Off                            ; Off                            ;
; Use smart compilation                                                 ; Off                            ; Off                            ;
+-----------------------------------------------------------------------+--------------------------------+--------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations                                                                                                                                                                                                                               ;
+-------------------------------------------------------------+-----------------+------------------+---------------------+-----------+----------------------------------------------------------------------------------------------------+------------------+
; Node                                                        ; Action          ; Operation        ; Reason              ; Node Port ; Destination Node                                                                                   ; Destination Port ;
+-------------------------------------------------------------+-----------------+------------------+---------------------+-----------+----------------------------------------------------------------------------------------------------+------------------+
; FIRInterp:inst8|LDout[7]                                    ; Packed Register ; Register Packing ; Timing optimization ; Q         ; mod:inst4|lpm_mult:Mult0|mult_mo01:auto_generated|mac_mult1                                        ; DATAA            ;
; FIRInterp:inst8|LDout[8]                                    ; Packed Register ; Register Packing ; Timing optimization ; Q         ; mod:inst4|lpm_mult:Mult0|mult_mo01:auto_generated|mac_mult1                                        ; DATAA            ;
; FIRInterp:inst8|LDout[9]                                    ; Packed Register ; Register Packing ; Timing optimization ; Q         ; mod:inst4|lpm_mult:Mult0|mult_mo01:auto_generated|mac_mult1                                        ; DATAA            ;
; FIRInterp:inst8|LDout[10]                                   ; Packed Register ; Register Packing ; Timing optimization ; Q         ; mod:inst4|lpm_mult:Mult0|mult_mo01:auto_generated|mac_mult1                                        ; DATAA            ;
; FIRInterp:inst8|LDout[11]                                   ; Packed Register ; Register Packing ; Timing optimization ; Q         ; mod:inst4|lpm_mult:Mult0|mult_mo01:auto_generated|mac_mult1                                        ; DATAA            ;
; FIRInterp:inst8|LDout[12]                                   ; Packed Register ; Register Packing ; Timing optimization ; Q         ; mod:inst4|lpm_mult:Mult0|mult_mo01:auto_generated|mac_mult1                                        ; DATAA            ;
; FIRInterp:inst8|LDout[13]                                   ; Packed Register ; Register Packing ; Timing optimization ; Q         ; mod:inst4|lpm_mult:Mult0|mult_mo01:auto_generated|mac_mult1                                        ; DATAA            ;
; FIRInterp:inst8|LDout[14]                                   ; Packed Register ; Register Packing ; Timing optimization ; Q         ; mod:inst4|lpm_mult:Mult0|mult_mo01:auto_generated|mac_mult1                                        ; DATAA            ;
; FIRInterp:inst8|LDout[15]                                   ; Packed Register ; Register Packing ; Timing optimization ; Q         ; mod:inst4|lpm_mult:Mult0|mult_mo01:auto_generated|mac_mult1                                        ; DATAA            ;
; FIRInterp:inst8|Md[0]                                       ; Packed Register ; Register Packing ; Timing optimization ; Q         ; FIRInterp:inst8|lpm_mult:Mult0|mult_jr01:auto_generated|mac_mult1                                  ; DATAA            ;
; FIRInterp:inst8|Md[1]                                       ; Packed Register ; Register Packing ; Timing optimization ; Q         ; FIRInterp:inst8|lpm_mult:Mult0|mult_jr01:auto_generated|mac_mult1                                  ; DATAA            ;
; FIRInterp:inst8|Md[2]                                       ; Packed Register ; Register Packing ; Timing optimization ; Q         ; FIRInterp:inst8|lpm_mult:Mult0|mult_jr01:auto_generated|mac_mult1                                  ; DATAA            ;
; FIRInterp:inst8|Md[3]                                       ; Packed Register ; Register Packing ; Timing optimization ; Q         ; FIRInterp:inst8|lpm_mult:Mult0|mult_jr01:auto_generated|mac_mult1                                  ; DATAA            ;
; FIRInterp:inst8|Md[4]                                       ; Packed Register ; Register Packing ; Timing optimization ; Q         ; FIRInterp:inst8|lpm_mult:Mult0|mult_jr01:auto_generated|mac_mult1                                  ; DATAA            ;
; FIRInterp:inst8|Md[5]                                       ; Packed Register ; Register Packing ; Timing optimization ; Q         ; FIRInterp:inst8|lpm_mult:Mult0|mult_jr01:auto_generated|mac_mult1                                  ; DATAA            ;
; FIRInterp:inst8|Md[6]                                       ; Packed Register ; Register Packing ; Timing optimization ; Q         ; FIRInterp:inst8|lpm_mult:Mult0|mult_jr01:auto_generated|mac_mult1                                  ; DATAA            ;
; FIRInterp:inst8|Md[7]                                       ; Packed Register ; Register Packing ; Timing optimization ; Q         ; FIRInterp:inst8|lpm_mult:Mult0|mult_jr01:auto_generated|mac_mult1                                  ; DATAA            ;