frecontr.v

来自「一种基于LUT的预失真方法。其中的一部分」· Verilog 代码 · 共 46 行

module frecontr(clk,rstn,freqword,fren);

parameter  	FREQ_BITS=32;


input 		clk,rstn;

output 		fren;
output		[FREQ_BITS-1:0]	 freqword;

reg         [5:0]            i;
reg         fren;
wire         [FREQ_BITS-1:0]	 freqword;

//assign freqword=32'h4B1EC4EC;
//assign freqword=32'h649534E0;//25.768
assign freqword=32'h48A4A630;//18.6m
//assign freqword=32'h1DCD6500;//7.625M
always@(posedge clk or negedge rstn)
	if (!rstn)
		begin
			i<=0;
			fren<=0;
			//freqword<=0;
		//	for (i=0;i<30;i=i+1)
				
		end
   else
		begin
			//fren<=1;
				begin 
						if(i<10)
						   begin 
								fren<=1;
								i<=i+1;
							//	freqword<=32'h4B1EC4EC;
			  				end
						else
							begin
							    fren<=0;
							
							end 
					end
		end		

endmodule