original_signal.tan.summary

来自「一种基于LUT的预失真方法。其中的一部分」· SUMMARY 代码 · 共 67 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 6.731 ns
From           : RstN
To             : mod:inst4|rposition[9]
From Clock     : --
To Clock       : clkin
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 5.243 ns
From           : mod:inst4|rfout[18]
To             : dataout[15]
From Clock     : clkin
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -3.632 ns
From           : RstN
To             : FIRInterp:inst8|we
From Clock     : --
To Clock       : clkin
Failed Paths   : 0

Type           : Clock Setup: 'altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]'
Slack          : 6.260 ns
Required Time  : 65.56 MHz ( period = 15.254 ns )
Actual Time    : 111.19 MHz ( period = 8.994 ns )
From           : FIRInterp:inst8|altsyncram:mem_rtl_0|altsyncram_csi1:auto_generated|ram_block1a0~portb_address_reg3
To             : FIRInterp:inst8|Md[9]
From Clock     : altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]
To Clock       : altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]
Failed Paths   : 0

Type           : Clock Hold: 'altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]'
Slack          : -2.079 ns
Required Time  : 65.56 MHz ( period = 15.254 ns )
Actual Time    : N/A
From           : CLK_ALL_GEN:inst5|count[4]
To             : FIRInterp:inst8|we
From Clock     : altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]
To Clock       : altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated|clk[0]
Failed Paths   : 21

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 21

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