clk_all_gen.v

来自「一种基于LUT的预失真方法。其中的一部分」· Verilog 代码 · 共 38 行

module		CLK_ALL_GEN(CLK,CLK_DIV2,CLK_DIV4,CLK_DIV8,CLK_DIV32,CLK_DIV64,
			CLK_DIV128,CLK_DIV256,CLK_DIV512);

input		CLK;
output		CLK_DIV2,
			CLK_DIV4,
			CLK_DIV8,
			CLK_DIV32,
			CLK_DIV64,
			CLK_DIV128,
			CLK_DIV256,
			CLK_DIV512;
wire		CLK_DIV2,
			CLK_DIV4,
			CLK_DIV8,
			CLK_DIV32,
			CLK_DIV64,
			CLK_DIV128,
			CLK_DIV256,
			CLK_DIV512;
			
reg[8:0]    count;
assign		CLK_DIV2	= count[0];
assign		CLK_DIV4	= count[1];
assign		CLK_DIV8	= count[2];
assign		CLK_DIV32	= count[4];
assign		CLK_DIV64	= count[5];
assign		CLK_DIV128	= count[6];
assign		CLK_DIV256	= count[7];
assign		CLK_DIV512	= count[8];

//always		@(negedge CLK)
always		@(posedge CLK)
begin
	count <= count + 9'b1;
end

endmodule