test123.v

Source codes for verilog fifo for spartan 3

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:42:12 01/21/2009 
// Design Name: 
// Module Name:    test123 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module test123();
wire [3:0] Q;
reg clk,reset;

ripple r1(clk, reset , Q);

initial begin

reset <= 0;
#5;
reset = 1;
#5;
reset = 0;
end

initial begin
clk <= 0;
end

always
begin
#5 clk <= ~clk;
end

endmodule