dff.v

来自「Source codes for verilog fifo for sparta」· Verilog 代码 · 共 37 行

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    17:07:50 01/21/2009 
// Design Name: 
// Module Name:    dff 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module dff(a,clk,reset,Q);

	input clk,a,reset;
	output Q;
	reg Q;
	
	always @ (posedge reset) begin
	Q <= 0;
	end
	
	always @ (posedge clk ) begin
	Q <= a;
	end


endmodule