alt_u_div_ote.tdf

用verilong hdl语言编写的数据采样程序

--alt_u_div DEVICE_FAMILY="Cyclone" LPM_PIPELINE=0 MAXIMIZE_SPEED=5 SKIP_BITS=0 WIDTH_D=10 WIDTH_N=13 WIDTH_Q=13 WIDTH_R=10 denominator numerator quotient remainder
--VERSION_BEGIN 6.0 cbx_cycloneii 2006:02:07:15:19:20:SJ cbx_lpm_abs 2006:01:02:19:20:00:SJ cbx_lpm_add_sub 2006:01:09:11:17:20:SJ cbx_lpm_divide 2006:01:18:17:01:10:SJ cbx_mgl 2006:05:17:10:06:16:SJ cbx_stratix 2006:05:17:09:28:32:SJ cbx_stratixii 2006:03:03:09:35:36:SJ cbx_util_mgl 2006:01:09:10:46:36:SJ  VERSION_END


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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
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--  without limitation, that your use is for the sole purpose of 
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FUNCTION add_sub_3dc (dataa[0..0], datab[0..0])
RETURNS ( cout, result[0..0]);
FUNCTION add_sub_4dc (dataa[1..0], datab[1..0])
RETURNS ( cout, result[1..0]);
FUNCTION add_sub_kec (dataa[10..0], datab[10..0])
RETURNS ( cout, result[10..0]);
FUNCTION add_sub_5dc (dataa[2..0], datab[2..0])
RETURNS ( cout, result[2..0]);
FUNCTION add_sub_6dc (dataa[3..0], datab[3..0])
RETURNS ( cout, result[3..0]);
FUNCTION add_sub_7dc (dataa[4..0], datab[4..0])
RETURNS ( cout, result[4..0]);
FUNCTION add_sub_8dc (dataa[5..0], datab[5..0])
RETURNS ( cout, result[5..0]);
FUNCTION add_sub_9dc (dataa[6..0], datab[6..0])
RETURNS ( cout, result[6..0]);
FUNCTION add_sub_adc (dataa[7..0], datab[7..0])
RETURNS ( cout, result[7..0]);
FUNCTION add_sub_bdc (dataa[8..0], datab[8..0])
RETURNS ( cout, result[8..0]);
FUNCTION add_sub_jec (dataa[9..0], datab[9..0])
RETURNS ( cout, result[9..0]);

--synthesis_resources = lut 30 
SUBDESIGN alt_u_div_ote
( 
	den_out[9..0]	:	output;
	denominator[9..0]	:	input;
	numerator[12..0]	:	input;
	quotient[12..0]	:	output;
	remainder[9..0]	:	output;
) 
VARIABLE 
	add_sub_0 : add_sub_3dc;
	add_sub_1 : add_sub_4dc;
	add_sub_10 : add_sub_kec;
	add_sub_11 : add_sub_kec;
	add_sub_12 : add_sub_kec;
	add_sub_2 : add_sub_5dc;
	add_sub_3 : add_sub_6dc;
	add_sub_4 : add_sub_7dc;
	add_sub_5 : add_sub_8dc;
	add_sub_6 : add_sub_9dc;
	add_sub_7 : add_sub_adc;