da_tlc5620.v

用verilong hdl语言编写的数据采样程序

module DA_TLC5620(
                  clk,
                  rst_n,
                  key,
                  CH451_DCLK,
                  CH451_DIN,
                  CH451_LOAD,
                  dac_clk,
                  dac_data,
                  dac_load,
                  dac_ldac
                 );

input            clk;
input            rst_n;
input[1:0]       key;
output           CH451_DCLK;
output           CH451_DIN;
output           CH451_LOAD;
output           dac_clk;
output           dac_data;
output           dac_load;
output           dac_ldac;


wire             write_n;
wire[10:0]       wr_data;
wire[7:0]        display_data0;
wire[7:0]        display_data1;
wire[7:0]        display_data2;
wire[7:0]        display_data3;

tlc5620 M1(
           .clk(clk),
           .rst(rst_n),
           .write_n(write_n),
           .wr_data(wr_data),
           .dac_clk(dac_clk),
           .dac_data(dac_data),
           .dac_load(dac_load),
           .dac_ldac(dac_ldac)
          );

dac_test M2(
            .clk(clk),
            .rst(rst_n),
            .key(key),
            .wr_n(write_n),
            .wr_data(wr_data),
            .display_data0(display_data3),
            .display_data1(display_data2),
            .display_data2(display_data1),
            .display_data3(display_data0),
           );
DISPLAY  M3(
            .clk(clk),
            .rst_n(rst_n),
            .data(
                  {
	               20'hfffff,
	               1'b0,display_data0[3:0],
                   1'b0,display_data1[3:0],
                   1'b0,display_data2[3:0],
                   1'b0,display_data3[3:0]
                  }
                 ),
            .CH451_DCLK(CH451_DCLK),
            .CH451_DIN(CH451_DIN),
            .CH451_LOAD(CH451_LOAD)
            );
endmodule