clk_pdiv.tdf

uart的vhdl实现

TITLE "Programmable Clock Frequency Divider"; 

%//////////////////
// INCLUDE FILES //
//////////////////%

INCLUDE "lpm_counter";
INCLUDE "lpm_compare";
INCLUDE "lpm_dff";

%////////////////////////////
// USER-DEFINED PARAMETERS //
////////////////////////////%

PARAMETERS
(
  WIDTH = 1
);

%/////////////////////
// INPUTS & OUTPUTS //
/////////////////////%

SUBDESIGN clk_pdiv
(
 CLK, D[WIDTH-1..0]		: INPUT;
 ENABLE					: INPUT = VCC;
 RESET					: INPUT = GND;

 OUT, Q[WIDTH-1..0]		: OUTPUT;
)

%/////////////////////////
// VARIABLE DEFINITIONS //
/////////////////////////%

VARIABLE
 COUNT				: NODE;

%//////////////////
// LOGIC SECTION //
//////////////////%

BEGIN

 ASSERT (WIDTH > 0)
 REPORT "Value of WIDTH parameter must be greater than 0"
 SEVERITY ERROR;

 COUNT	= LPM_COMPARE(.Dataa[] = Q[], .Datab[] = D[])
          WITH (LPM_WIDTH=WIDTH)
          RETURNS (.aeb);
 Q[]	= LPM_COUNTER (.CLOCK = CLK, .CLK_EN = ENABLE, .ACLR = RESET, .SCLR = COUNT)
          WITH (LPM_WIDTH=WIDTH)
          RETURNS (.q[]);
 OUT	= LPM_DFF (COUNT, CLK, ENABLE,,,,,,,,)
          WITH (LPM_WIDTH=1)
          RETURNS (.q[]);

END;